Abstract: A mounting structure of a thermal management module for a vehicle according to an embodiment of the present disclosure includes: front side members extending along a length direction of a vehicle and disposed on left and right sides of the vehicle, respectively, in a width direction of the vehicle; a dash reinforcement crossmember extending along the width direction of the vehicle and coupled to rear ends of the front side members on the left and right sides based on a front and rear direction of the vehicle; a crossmember dividing a space formed by the front side members into two spaces in the front and rear direction of the vehicle; and at least one mounting bracket, on which the thermal management module is mounted, configured to mount the thermal management module in one of the two spaces divided by the crossmember.

Abstract: A mounting structure of a thermal management module for a vehicle according to an embodiment of the present disclosure includes: front side members extending along a length direction of a vehicle and disposed on left and right sides of the vehicle, respectively, in a width direction of the vehicle; a dash reinforcement crossmember extending along the width direction of the vehicle and coupled to rear ends of the front side members on the left and right sides based on a front and rear direction of the vehicle; a crossmember dividing a space formed by the front side members into two spaces in the front and rear direction of the vehicle; and at least one mounting bracket, on which the thermal management module is mounted, configured to mount the thermal management module in one of the two spaces divided by the crossmember.

Abstract: A mounting structure of a thermal management module for a vehicle according to an embodiment of the present disclosure includes: front side members extending along a length direction of a vehicle and disposed on left and right sides of the vehicle, respectively, in a width direction of the vehicle; a dash reinforcement crossmember extending along the width direction of the vehicle and coupled to rear ends of the front side members on the left and right sides based on a front and rear direction of the vehicle; a crossmember dividing a space formed by the front side members into two spaces in the front and rear direction of the vehicle; and at least one mounting bracket, on which the thermal management module is mounted, configured to mount the thermal management module in one of the two spaces divided by the crossmember.

Abstract: Provided is an integrated heat exchanger including a header tank in which a gasket is interposed between the header and the tank to seal a portion that the header and the tank are coupled to each other, wherein an inner space of the header tank is partitioned such that a first space portion formed between regions in which the heat exchange medium flows is formed to be in communication with an external region of the header tank through a heat exchange medium discharging means formed at a portion that the header and the tank are coupled to each other, thereby preventing the heat exchange mediums from being leaked between two heat exchange portions and to detect a leakage of the heat exchange medium even when the leakage of the heat exchange medium occurs.

Abstract: Provided is an integrated heat exchanger including a header tank in which a gasket is interposed between the header and the tank to seal a portion that the header and the tank are coupled to each other, wherein an inner space of the header tank is partitioned such that a first space portion formed between regions in which the heat exchange medium flows is formed to be in communication with an external region of the header tank through a heat exchange medium discharging means formed at a portion that the header and the tank are coupled to each other, thereby preventing the heat exchange mediums from being leaked between two heat exchange portions and to detect a leakage of the heat exchange medium even when the leakage of the heat exchange medium occurs.

Abstract: The present invention relates to a system for analyzing molecular sequences, which is capable of decoding unit molecules constituting various biopolymers on a real-time basis using nanochannels. A control electrode serves to control the unit molecules passing along the channel such that the velocity of movement, arrangement, and directivity of the unit molecules can be rendered uniform. Particularly, at least four probe electrodes are separately formed in the case of decoding ss-DNA base molecules. Each probe electrode is coated with four different types of DNA base molecules to maximize detection efficiency through the interaction with complementary base molecules moving along the inside of the channel.

Abstract: The present system relates to a system architecture that uses a single electron transistor (SET) to analyze base sequences of deoxyribonucleic acid (DNA) at ultra high speed in real time. DNA represents the entire body of genetic information and consists of nucleotide units. There are a total of four types of nucleotides, and each nucleotide consists of an identical pentose (deoxyribose), phosphate group, and one of four types of bases (Adenine: A, Guanine: G, Cytosine: C, Thymine: T). A and G are purines having a bicyclic structure while C and T are pyrimidines having a monocyclic structure. Each has a different atomic arrangement, which signifies a different charge distribution from one another. Therefore, a system comprising a single electron transistor that is very sensitive to charges, a probe of a very small size that reacts to one nucleotide very effectively, and an extended gate that connects the SET with the probe, can be used to analyze DNA base sequences at ultra high speed in real time.

Abstract: The present invention relates to a multi-quantum dot device and a method of manufacturing the multi-quantum dot device.

Abstract: The present invention relates to a multi-quantum dot device and a method of manufacturing the multi-quantum dot device.

Abstract: The present invention relates to a method of fabricating a nanoscale multi-junction quantum dot device wherein it can minimize constraints depending on the number or shape of patterns and a line width, and in particular, overcome shortcomings depending on the proximity effect occurring between patterns while employing the advantages of electron beam lithography to the utmost by forming a new conductive layer between the patterns and utilizing it as a new pattern.

Abstract: The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor operating at room temperature and a method of manufacturing the same, which are capable of minimizing influence of the gate voltage on tunneling barriers and effectively controlling the electric potential of a quantum dot (QD), by forming the quantum dot using a trenched nano-wire structure and forming the gate to wrap most of the way around the quantum dot.

Abstract: Provided is a multi-valued dynamic random access memory (DRAM) cell using a single electron transistor (SET). The multi-valued DRAM cell using the SET applies different refresh signals to a load current transistor for controlling current supply to the SET and a voltage control transistor for controlling a terminal voltage of the SET and refreshes a data value stored in the SET by a predetermined period to reduce standby current and stably supply a voltage low enough to satisfy a coulomb-blockade condition to the terminal of the SET.

Abstract: Provided herein is an MV DRAM device for storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, where the gate of the transistor is connected to the ground voltage.

Abstract: The present system relates to a system architecture that uses a single electron transistor (SET) to analyze base sequences of deoxyribonucleic acid (DNA) at ultra high speed in real time. DNA represents the entire body of genetic information and consists of nucleotide units. There are a total of four types of nucleotides, and each nucleotide consists of an identical pentose (deoxyribose), phosphate group, and one of four types of bases (Adenine: A, Guanine: G, Cytosine: C, Thymine: T). A and G are purines having a bicyclic structure while C and T are pyrimidines having a monocyclic structure. Each has a different atomic arrangement, which signifies a different charge distribution from one another. Therefore, a system comprising a single electron transistor that is very sensitive to charges, a probe of a very small size that reacts to one nucleotide very effectively, and an extended gate that connects the SET with the probe, can be used to analyze DNA base sequences at ultra high speed in real time.

Abstract: The present invention relates to a room temperature-operating single-electron device and a fabrication method thereof, and more particularly, to a room temperature-operating single-electron device in which a plurality of metal silicide dots formed serially is used as multiple quantum dots, and a fabrication method thereof.

Abstract: The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor operating at room temperature and a method of manufacturing the same, which are capable of minimizing influence of the gate voltage on tunneling barriers and effectively controlling the electric potential of a quantum dot (QD), by forming the quantum dot using a trenched nano-wire structure and forming the gate to wrap most of the way around the quantum dot.

Abstract: The present invention relates to a single electron transistor operating at room temperature and a manufacturing method for same. More particularly, the present invention relates to a single electron transistor operating at room temperature, in which a quantum dot or a silicide quantum dot using a nanostructure is formed and a gate is positioned on the quantum dot so as to minimize influence on a tunneling barrier and achieve improved effectiveness in electric potential control for the quantum dot and operating efficiency of the transistor, and a manufacturing method for same.

Abstract: The present invention relates to a room temperature-operating single-electron device and a fabrication method thereof, and more particularly, to a room temperature-operating single-electron device in which a plurality of metal silicide dots formed serially is used as multiple quantum dots, and a fabrication method thereof.

Abstract: The present invention relates to a flexible multi-functional logic circuit which switches a current direction to a serial or parallel direction using at least two single electron transistors (SETs) having the same pattern and as many field effect transistors (FETs) as the number of the single electron transistors and performs operations on multi-valued signals using Coulomb oscillation that is the unique characteristic of SET to enable conversion of a single logic circuit to four basic logic circuits of NAND, OR, NOR and AND gates and a device using the same.

Abstract: A method and an apparatus for supporting a discontinuous reception (DRX) operation in a Node B in a mobile communication system are provided. The method includes defining a second System Frame Number (SFN) where one cycle of a first SFN corresponds to one bit, transmitting information on the second SFN to a User Equipment (UE), determining a second SFN which is used to transmit a paging signal to the UE, determining a first SFN which is used to transmit the paging signal in the determined second SFN, and transmitting the paging signal to the UE at the determined first SFN.