Patents by Inventor Jung-Chang Chen
Jung-Chang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170556Abstract: A method for forming a semiconductor structure is provided. The method includes forming a spacer layer along a first fin structure and a second fin structure, etching a first portion of the spacer layer and the first fin structure to form first fin spacers and a first recess between the first fin spacers, etching a second portion of the spacer layer and the second fin structure to form second fin spacers and a second recess between the second fin spacers, and forming a first source/drain feature in the first recess and a second source/drain feature in the second recess. The second fin structure is wider than the first fin structure. The first fin spacers have a first height, and the second fin spacers have a second height that is greater than the first height.Type: ApplicationFiled: February 20, 2023Publication date: May 23, 2024Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
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Publication number: 20240170337Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Zhi-Chang LIN, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Kuan-Ting PAN, Jung-Hung CHANG, Lo-Heng CHANG, Chien Ning YAO
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Patent number: 11967594Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.Type: GrantFiled: August 10, 2022Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20240096895Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
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Patent number: 11929287Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.Type: GrantFiled: April 23, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Kuan-Ting Pan, Jung-Hung Chang, Lo-Heng Chang, Chien Ning Yao
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Patent number: 11916122Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.Type: GrantFiled: July 8, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zhi-Chang Lin, Kuan-Ting Pan, Shih-Cheng Chen, Jung-Hung Chang, Lo-Heng Chang, Chien-Ning Yao, Kuo-Cheng Chiang
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Patent number: 9727049Abstract: The present disclosure provides various methods for tool condition monitoring, including systems for implementing such monitoring. An exemplary method includes receiving data associated with a process performed on wafers by an integrated circuit manufacturing process tool; and monitoring a condition of the integrated circuit manufacturing process tool using the data. The monitoring includes evaluating the data based on an abnormality identification criterion, an abnormality filtering criterion, and an abnormality threshold to determine whether the data meets an alarm threshold. The method may further include issuing an alarm when the data meets the alarm threshold.Type: GrantFiled: September 4, 2012Date of Patent: August 8, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Tong Ho, Po-Feng Tsai, Jung-Chang Chen, Tze-Liang Lee, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
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Publication number: 20140067324Abstract: The present disclosure provides various methods for tool condition monitoring, including systems for implementing such monitoring. An exemplary method includes receiving data associated with a process performed on wafers by an integrated circuit manufacturing process tool; and monitoring a condition of the integrated circuit manufacturing process tool using the data. The monitoring includes evaluating the data based on an abnormality identification criterion, an abnormality filtering criterion, and an abnormality threshold to determine whether the data meets an alarm threshold. The method may further include issuing an alarm when the data meets the alarm threshold.Type: ApplicationFiled: September 4, 2012Publication date: March 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Tong Ho, Po-Feng Tsai, Jung-Chang Chen, Tze-Liang Lee, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
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Patent number: 6851168Abstract: A clamp for quickly, effectively and safely removing a cathode collar from an HDP deposition chamber for routine maintenance, cleaning or replacement of the collar. The clamp includes a pair of clamp plates which are capable of pivoting movement on respective ends of a connecting rod. A clamp shoe for gripping a corresponding edge of the annular collar is provided on the bottom end of each clamp plate, and a turnbuckle is fitted with a pair of threaded shafts which engage the upper end portions of the respective clamp plates. By rotating the turnbuckle, the threaded shafts are advanced away from each other against the clamp plates, which pivot on the connecting rod and cause the clamp shoes to tightly engage respective edges of the collar. The clamp is grasped to lift the collar from the chamber and replace the collar in the chamber after cleaning or maintenance.Type: GrantFiled: June 19, 2002Date of Patent: February 8, 2005Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Wen-Shan Chang, Jung-Chang Chen, Shih-Chang Hsu, Li-Chung Wang, Cheng-Chia Kuo, Jong-Min Lin, Kuo-Ming Yu, Da-Hsiang Chou, Kuo-Chuan Chen, Ming-Te Chen
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Publication number: 20030233746Abstract: A clamp for quickly, effectively and safely removing a cathode collar from an HDP deposition chamber for routine maintenance, cleaning or replacement of the collar. The clamp includes a pair of clamp plates which are capable of pivoting movement on respective ends of a connecting rod. A clamp shoe for gripping a corresponding edge of the annular collar is provided on the bottom end of each clamp plate, and a turnbuckle is fitted with a pair of threaded shafts which engage the upper end portions of the respective clamp plates. By rotating the turnbuckle, the threaded shafts are advanced away from each other against the clamp plates, which pivot on the connecting rod and cause the clamp shoes to tightly engage respective edges of the collar. The clamp is grasped to lift the collar from the chamber and replace the collar in the chamber after cleaning or maintenance.Type: ApplicationFiled: June 19, 2002Publication date: December 25, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Shan Chang, Jung-Chang Chen, Shih-Chang Hsu, Li-Chung Wang, Cheng-Chia Kuo, Jong-Min Lin, Kuo-Ming Yu, Da-Hsiang Chou, Kuo-Chuan Chen, Ming-Te Chen
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Patent number: 5896080Abstract: A thermal fuse includes a resilient coil portion with a turn of at least 360.degree.. Two spring arms have two upper portions connected to and integrally formed with two ends of the coil portion, and two lower portions extending from the upper portions and formed with two contact locations for connection to two circuit contacts of the circuit board. At least one of the contact locations is to be soldered on the circuit board. During the connection of the contact locations to the circuit contacts, the lower portions are kept in a tensed state by moving the contact locations toward each other so as to generate a biasing force to bias the lower portions away from each other.Type: GrantFiled: April 10, 1998Date of Patent: April 20, 1999Assignee: Kun-Ming TsaiInventor: Jung-Chang Chen
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Patent number: D358903Type: GrantFiled: June 27, 1994Date of Patent: May 30, 1995Assignee: Wan Chang Precision Industries Co., Ltd.Inventor: Jung-Chang Chen
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Patent number: D408255Type: GrantFiled: April 15, 1998Date of Patent: April 20, 1999Inventor: Jung-Chang Chen
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Patent number: D1016313Type: GrantFiled: February 14, 2022Date of Patent: February 27, 2024Assignee: Acer IncorporatedInventors: Wei-Chang Chen, Jung-Wei Tsao
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Patent number: D1016822Type: GrantFiled: December 1, 2021Date of Patent: March 5, 2024Assignee: Acer IncorporatedInventors: Wei-Chang Chen, Jung-Wei Tsao
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Patent number: D1023378Type: GrantFiled: February 22, 2022Date of Patent: April 16, 2024Assignee: Acer IncorporatedInventors: Wei-Chang Chen, Jung-Wei Tsao