Patents by Inventor Jung Chou
Jung Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12277379Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: GrantFiled: August 10, 2023Date of Patent: April 15, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
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Patent number: 12259455Abstract: Calibrating a battery including identifying a historical discharge rate of the battery; segmenting the historical discharge rate of the battery into regions; determining, based on the historical discharge rate of the battery, a first historical charge capacity of the battery for a first region and a second historical charge capacity of the battery for a second region; discharging, at an updated discharge rate, the battery from a first threshold voltage to a second threshold voltage; calculating, based on the updated discharge rate, a first updated charge capacity of the battery for the first region; determining a full charge capacity of the battery based on i) the first updated charge capacity of the battery for the first region and ii) the second historical charge capacity of the battery for the second region; adjusting a charging current of the battery based on the determined full charge capacity of the battery.Type: GrantFiled: March 30, 2023Date of Patent: March 25, 2025Assignee: Dell Products L.P.Inventors: Pei-Ying Lin, Adolfo S. Montero, Chien-Hao Chiu, Shuo-Jung Chou
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Patent number: 12216981Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: GrantFiled: August 10, 2023Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
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Publication number: 20240353494Abstract: An information handling system determines that a relative state of charge (RSOC) on the battery is above a threshold RSOC. When the RSOC is above the RSOC threshold, the system determines that an initial temperature of the battery is within a first range, determines that a time rate of temperature increase on the battery is greater than a first slope, the first slope being determined based upon the first range, and discharges the battery to below the threshold RSOC in response to the determining that the time rate of temperature increase is greater than the first slope.Type: ApplicationFiled: April 21, 2023Publication date: October 24, 2024Inventors: Shuo-Jung Chou, Tsz Leung, Chia-Fa Chang, Chien-Hao Chiu, Wen-Yung Chang, Yu-Chi Chin
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Publication number: 20240329178Abstract: Calibrating a battery including identifying a historical discharge rate of the battery; segmenting the historical discharge rate of the battery into regions; determining, based on the historical discharge rate of the battery, a first historical charge capacity of the battery for a first region and a second historical charge capacity of the battery for a second region; discharging, at an updated discharge rate, the battery from a first threshold voltage to a second threshold voltage; calculating, based on the updated discharge rate, a first updated charge capacity of the battery for the first region; determining a full charge capacity of the battery based on i) the first updated charge capacity of the battery for the first region and ii) the second historical charge capacity of the battery for the second region; adjusting a charging current of the battery based on the determined full charge capacity of the battery.Type: ApplicationFiled: March 30, 2023Publication date: October 3, 2024Inventors: PEI-YING LIN, ADOLFO S. MONTERO, CHIEN-HAO CHIU, SHUO-JUNG CHOU
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Publication number: 20240274561Abstract: An interconnect structure includes a plurality of first pads, a plurality of second pads, and a plurality of conductive lines. The first pads are arranged to form a first column-and-row array, and the second pads are arranged to form a second column-and-row array. The first column-and-row array, the second column-and-row array and the conductive lines are disposed in a same layer. The first pads in adjacent rows in the first column-and-row array are separated from each other by a first vertical distance from a plan view, the second pads in adjacent rows in the second column-and-row array are separated from each other by a second vertical distance from the plan view. A sum of widths of the conductive lines electrically connecting the first pads and the second pads in the same row is less than the first vertical distance and the second vertical distance from the plan view.Type: ApplicationFiled: April 29, 2024Publication date: August 15, 2024Inventors: JUNG-CHOU TSAI, FONG-YUAN CHANG, PO-HSIANG HUANG, CHIN-CHOU LIU, YI-KAN CHENG
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Patent number: 12045108Abstract: An electronic apparatus and a load adjusting method thereof are provided. The method includes the following steps. Powering of an external power supply is detected. A self-power consumption time of the battery from a full capacity to a preset capacity is calculated and recorded when the powering of the external power supply is detected. A first average value of multiple self-power consumption times recorded within a preset period from a current time is calculated, and the first average value is compared with a second average value of the self-power consumption times of a previous preset period of the preset period. A value of a power limit for controlling the electronic apparatus to enter a load adjusting state is adjusted according to a comparison result.Type: GrantFiled: July 18, 2022Date of Patent: July 23, 2024Assignee: Acer IncorporatedInventors: Shuo-Jung Chou, Chuan-Jung Wang, Chih-Chiang Chen
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Publication number: 20240191388Abstract: An electrolytic polishing treatment method for a nickel-based alloy workpiece made by lamination manufacturing comprises the following steps. Step (A) comprises performing a sandblasting treatment on the nickel-based alloy workpiece, followed by ultrasonic oscillation of the sandblasted nickel-based alloy workpiece in an oxalic acid solution. Step (B) comprises placing the nickel-based alloy workpiece in an electrolyte solution containing methanol, sulfuric acid, and perchloric acid and performing electrolytic polishing on the nickel-based alloy workpiece at a constant voltage after step (A). The processes of oxalic acid activation and electrolytic polishing are used to avoid the problems of residual stress and processing directionality caused by conventional mechanical processing and make the surface properties of the entire workpiece uniform.Type: ApplicationFiled: December 7, 2023Publication date: June 13, 2024Inventors: CHUN-HSIANG KAO, YI-CHERNG FERNG, YING-SUN HUANG, KUO-KUANG JEN, SHUN-YI JIAN, CHIA-YU LEE, JUNG-CHOU HUNG, PO-JEN YANG
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Patent number: 12002776Abstract: An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mth row extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The second pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nth conductive lines.Type: GrantFiled: July 12, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jung-Chou Tsai, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu, Yi-Kan Cheng
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Patent number: 11949270Abstract: A battery module for monitoring and suppressing battery swelling and interacting with a charging device includes a battery cell disposed in a nonconductive housing, a conductive label affixed to the nonconductive housing, a switch, and a controller. The battery cell is charged via a supply voltage from a charging device. The switch is coupled between the battery cell and the conductive label. The controller detects a resistance variation value ?R of the conductive label as result of swelling of the nonconductive housing, and generates a corresponding control voltage. As the resistance of the conductive label increases, the supply voltage may be adjusted downward according to the control voltage. If the resistance variation value ?R conductive label is greater than or equal to a predetermined threshold, the controller closes the switch, and the battery cell may then fully discharge through the conductive label.Type: GrantFiled: October 18, 2021Date of Patent: April 2, 2024Assignee: ACER INCORPORATEDInventors: Shuo-Jung Chou, Chuan-Jung Wang, Chih-Chiang Chen
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Publication number: 20240095439Abstract: Disclosed are semiconductor devices having an interconnection pattern that includes a plurality of parallel conductors including a first conductor aligned with a first axis and a first dummy pattern aligned with a second axis on a first side of the first axis and offset from the first axis by an axis offset distance LAO in which the first dummy pattern includes N dummy conductors having a first dummy conductor length LDC with the dummy conductors being separated by a dummy conductor-to-dummy conductor spacing EED.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Inventors: Wei-Yi HU, Chih-Ming CHAO, Jung-Chou TSAI
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Patent number: 11886263Abstract: A signal re-driving device, a data storage system and a mode control method are provided. The method includes the following steps. A first signal is received via a receiving circuit of the signal re-driving device. An analog signal feature is detected the receiving circuit. A first mode is entered according to the analog signal feature. The first signal is modulated and a second signal is outputted in the first mode. The second signal is sent via a sending circuit of the signal re-driving device. A digital signal feature is detected via the receiving circuit. And, the first mode is switched to a second mode according to the digital signal feature.Type: GrantFiled: August 27, 2021Date of Patent: January 30, 2024Assignee: PHISON ELECTRONICS CORP.Inventors: Po-Jung Chou, Sheng-Wen Chen, Chung-Kuang Chen
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Publication number: 20230394219Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: ApplicationFiled: August 10, 2023Publication date: December 7, 2023Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
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Publication number: 20230385522Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
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Patent number: 11790151Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: GrantFiled: August 10, 2022Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
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Patent number: 11775727Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: GrantFiled: March 12, 2019Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
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Publication number: 20230179009Abstract: A charging method with hysteresis includes the steps of: performing a pre-determination process to check whether the battery temperature of a battery cell is higher than or equal to a predetermined temperature; if the battery temperature is higher than or equal to the predetermined temperature, enabling a hysteresis mechanism; Upon the hysteresis mechanism, initially charging the battery cell with a small charging current; performing a first determination process to check whether the battery temperature decreases to a first threshold temperature; if the battery temperature decreases to the first threshold temperature, charging the battery cell with a large charging current; performing a second determination process to check whether the battery temperature increases to a second threshold temperature; and if the battery temperature increases to the second threshold temperature, charging the battery cell with the small charging current.Type: ApplicationFiled: March 21, 2022Publication date: June 8, 2023Inventors: Shuo-Jung CHOU, Chuan-Jung WANG, Chih-Chiang CHEN
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Publication number: 20230152870Abstract: An electronic apparatus and a load adjusting method thereof are provided. The method includes the following steps. Powering of an external power supply is detected. A self-power consumption time of the battery from a full capacity to a preset capacity is calculated and recorded when the powering of the external power supply is detected. A first average value of multiple self-power consumption times recorded within a preset period from a current time is calculated, and the first average value is compared with a second average value of the self-power consumption times of a previous preset period of the preset period. A value of a power limit for controlling the electronic apparatus to enter a load adjusting state is adjusted according to a comparison result.Type: ApplicationFiled: July 18, 2022Publication date: May 18, 2023Applicant: Acer IncorporatedInventors: Shuo-Jung Chou, Chuan-Jung Wang, Chih-Chiang Chen
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Publication number: 20230142853Abstract: Disclosed are semiconductor devices having an interconnection pattern that includes a plurality of parallel conductors including a first conductor aligned with a first axis and a first dummy pattern aligned with a second axis on a first side of the first axis and offset from the first axis by an axis offset distance LAO in which the first dummy pattern includes N dummy conductors having a first dummy conductor length LDC with the dummy conductors being separated by a dummy conductor-to-dummy conductor spacing EED.Type: ApplicationFiled: January 11, 2023Publication date: May 11, 2023Inventors: Wei-Yi HU, Chih-Ming CHAO, Jung-Chou TSAI
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Publication number: 20230035428Abstract: A signal re-driving device, a data storage system and a mode control method are provided. The method includes the following steps. A first signal is received via a receiving circuit of the signal re-driving device. An analog signal feature is detected the receiving circuit. A first mode is entered according to the analog signal feature. The first signal is modulated and a second signal is outputted in the first mode. The second signal is sent via a sending circuit of the signal re-driving device. A digital signal feature is detected via the receiving circuit. And, the first mode is switched to a second mode according to the digital signal feature.Type: ApplicationFiled: August 27, 2021Publication date: February 2, 2023Applicant: PHISON ELECTRONICS CORP.Inventors: Po-Jung Chou, Sheng-Wen Chen, Chung-Kuang Chen