Patents by Inventor Jung-Dal Choi

Jung-Dal Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11037953
    Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung Bo Shim, Jung Dal Choi
  • Publication number: 20210020203
    Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.
    Type: Application
    Filed: November 13, 2019
    Publication date: January 21, 2021
    Applicant: SK hynix Inc.
    Inventors: Jung Dal CHOI, Jung Shik JANG, Jin Kook KIM, Dong Sun SHEEN, Se Young OH, Ki Hong LEE, Dong Hun LEE, Sung Hoon LEE, Sung Yong CHUNG
  • Patent number: 10644026
    Abstract: A semiconductor device includes: a stack structure; a source connection structure penetrating the stack structure; n first channel rows located at one side of the source connection structure, the n first channel rows including channel patterns; and n+k second channel rows located at the other side of the source connection structure, at least one channel row among the n+k second channel rows including dummy channel patterns, wherein the n and k are integers.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventors: Nam Jae Lee, Jung Dal Choi
  • Publication number: 20190363100
    Abstract: A semiconductor device includes: a stack structure; a source connection structure penetrating the stack structure; n first channel rows located at one side of the source connection structure, the n first channel rows including channel patterns; and n+k second channel rows located at the other side of the source connection structure, at least one channel row among the n+k second channel rows including dummy channel patterns, wherein the n and k are integers.
    Type: Application
    Filed: December 21, 2018
    Publication date: November 28, 2019
    Inventors: Nam Jae LEE, Jung Dal CHOI
  • Publication number: 20190288003
    Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Inventors: Sung Bo Shim, Jung Dal Choi
  • Patent number: 10355013
    Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Sung Bo Shim, Jung Dal Choi
  • Publication number: 20180323207
    Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.
    Type: Application
    Filed: December 21, 2017
    Publication date: November 8, 2018
    Inventors: Sung Bo SHIM, Jung Dal CHOI
  • Patent number: 9761314
    Abstract: A non-volatile memory device includes a semiconductor substrate and a tunnel insulating layer and a gate electrode. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than in the blocking insulation layer. A minimum field at a blocking insulation layer can be stronger than at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than through the blocking insulation layer.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: September 12, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hyun Lee, Jung-Dal Choi
  • Patent number: 9564435
    Abstract: A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-ae Chung, Jung-dal Choi, Toshiro Nakanishi, Yu-bin Kim, Gab-jin Nam, Dong-kyu Lee, Guangfan Jiao
  • Publication number: 20160329333
    Abstract: A semiconductor device includes a substrate, a strain-relaxed buffer layer on the substrate, at least one well in the strain-relaxed buffer layer, a first channel layer on the strain-relaxed buffer layer, and a second channel layer on the well. A lattice constant of material constituting the first well is less than a lattice constant of the material constituting the strain-relaxed buffer layer, but a lattice constant of material constituting the second well is greater than the lattice constant of the material constituting the strain-relaxed buffer layer.
    Type: Application
    Filed: July 18, 2016
    Publication date: November 10, 2016
    Inventors: DONG-KYU LEE, JAE-HWAN LEE, TAE-YONG KWON, SANG-SU KIM, JUNG-DAL CHOI
  • Patent number: 9450025
    Abstract: A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: September 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Jung, Youn-Seon Kang, Jung-Dal Choi
  • Patent number: 9450049
    Abstract: A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: September 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Yong Kwon, Sang-Su Kim, Jung-Gil Yang, Jung-Dal Choi
  • Publication number: 20160247819
    Abstract: A semiconductor device includes a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.
    Type: Application
    Filed: May 5, 2016
    Publication date: August 25, 2016
    Inventors: JAE-SUNG SIM, JUNG-DAL CHOI
  • Patent number: 9425198
    Abstract: A semiconductor device includes a substrate, a strain-relaxed buffer layer on the substrate, at least one well in the strain-relaxed buffer layer, a first channel layer on the strain-relaxed buffer layer, and a second channel layer on the well. A lattice constant of material constituting the first well is less than a lattice constant of the material constituting the strain-relaxed buffer layer, but a lattice constant of material constituting the second well is greater than the lattice constant of the material constituting the strain-relaxed buffer layer.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Kyu Lee, Jae-Hwan Lee, Tae-Yong Kwon, Sang-Su Kim, Jung-Dal Choi
  • Patent number: 9391269
    Abstract: A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: July 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Moo Lee, Youn-Seon Kang, Seung-Jae Jung, Jung-Dal Choi
  • Patent number: 9391134
    Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: July 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Jae Yang, Sang-Su Kim, Jae-Hwan Lee, Jung-Dal Choi
  • Patent number: 9385138
    Abstract: In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: July 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Sung Sim, Jung-Dal Choi
  • Patent number: 9373664
    Abstract: A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: June 21, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Jun Seong, Youn-Seon Kang, Seung-Jae Jung, Jung-Dal Choi
  • Patent number: 9349879
    Abstract: A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: May 24, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Hyung Kim, Chang-Seok Kang, Sung-Il Chang, Jung-Dal Choi
  • Patent number: 9318419
    Abstract: Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sok-Won Lee, Joon-Hee Lee, Jung-Dal Choi, Seong-Min Jo