Abstract: The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first stack structure, a plurality of first slits passing through the first stack structure in a vertical direction and extending in a first horizontal direction orthogonal to the vertical direction, a first source line layer contacting an a top portion of the first stack structure, a second source line layer directly contacting the first source line layer, a second stack structure contacting the second source line layer and overlapping with the first stack structure in the vertical direction, and a plurality of second slits passing through the second stack structure in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: The present discloses provides a memory device and a method of operating the memory device. The memory device includes first main plugs formed in a vertical direction over a substrate and arranged in a first direction, second main plugs, third main plugs arranged between the first and second main plugs, the third main plugs adjacent to the first and second main plugs, and bit lines above the first to third main plugs, wherein each of the first to third main plugs includes first and second sub-plugs facing each other, wherein portions of the first and second sub-plugs included in each of the first and third main plugs are coupled to different select lines, and wherein portions of the first and second sub-plugs included in each of the second and third main plugs are coupled to different select lines.

Abstract: The present disclosure relates to a semiconductor memory device. The semiconductor memory device includes a gate stack, a hole penetrating the gate stack, and a channel structure. The hole has an undercut region defined on a sidewall thereof. The channel structure covers a portion of the undercut region and opens another portion of the undercut region.

Abstract: A semiconductor device may include a gate structure, a source structure that is disposed on the gate structure, channel structures that extend into the source structure through the gate structure and include a channel layer and a memory layer surrounding the channel layer, the memory layer including a cut area that exposes the channel layer, and a slit structure that extends into the source structure through the gate structure between the channel structures, an upper surface of the slit structure being disposed at a lower level than the cut area.

Abstract: In a method of manufacturing a semiconductor device, an additional, induced-stress-limiting structure may be provided on a surface, which opposes stress that can be induced in a semiconductor device during its manufacturing processes. Such a stress compensation layer may be formed on a surface to compensate a stress applied to the rest of structure.

Abstract: A memory device includes: a memory cell array including a plurality of cell plugs; a first slit isolating the memory cell array into a plurality of memory regions, the first slit extending in a first direction; and second slits penetrating the plurality of memory regions, the second slits being arranged to be spaced apart from each other in a second direction intersecting the first direction. Gate lines included in each of the plurality of memory regions may be isolated from each other by the first slit. Each gate line located in the same layer among the gate lines included in each of the plurality of memory regions may extend through a first connection region between the second slits for each corresponding memory region.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: A semiconductor device may include: a first gate structure including a plurality of first conductive layers that are alternately stacked with a plurality of first insulating layers; a second gate structure including a plurality of second conductive layers that are alternately stacked with a plurality of second insulating layers; a third gate structure including third conductive layers that are alternately stacked with a plurality of third insulating layers; and a first contact plug extending into the first gate structure through the third gate structure and the second gate structure, the first contact plug connected to a first of the plurality of first conductive layers, and the first contact plug including a first inflection portion located at an interface between the second gate structure and the third gate structure.

Abstract: The present discloses provides a memory device and a method of operating the memory device. The memory device includes first main plugs formed in a vertical direction over a substrate and arranged in a first direction, second main plugs, third main plugs arranged between the first and second main plugs, the third main plugs adjacent to the first and second main plugs, and bit lines above the first to third main plugs, wherein each of the first to third main plugs includes first and second sub-plugs facing each other, wherein portions of the first and second sub-plugs included in each of the first and third main plugs are coupled to different select lines, and wherein portions of the first and second sub-plugs included in each of the second and third main plugs are coupled to different select lines.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device including a stacked body including conductive patterns and insulating patterns that are alternately stacked, a filling layer configured to pass through the stacked body, a first channel layer configured to pass through the stacked body and coupled to the filling layer, a second channel layer configured to pass through the stacked body and coupled to the filling layer, a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer, a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer, and a memory layer surrounding the filling layer, the first and second channel layers, and the first and second interposed layers.

Abstract: A semiconductor device includes a gate structure including conductive layers and insulating layers that are alternately stacked. The semiconductor device also includes an insulating core located in the gate structure and including a long axis and a short axis. The semiconductor device further includes a first channel pattern and a second channel pattern surrounding the insulating core and located to face each other along the long axis. The semiconductor device additionally includes a barrier pattern surrounding the first channel pattern and the second channel pattern and having different thicknesses along the long axis and the short axis.

Abstract: A semiconductor device includes a supporter including a plurality of stairs, a gate structure including gate lines that are stacked on the supporter, wherein the gate lines include pads, and the pads are disposed over the plurality of stairs, first contact plugs that are connected to the pads, and channel structures that extend through the gate structure.

Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a plurality of conductive layers stacked to be spaced apart from each other in a first direction; a channel hole extending in the first direction to penetrate the plurality of conductive layers; two or more channel patterns disposed to be spaced apart from each other along a sidewall of the channel hole; and two or more memory patterns disposed to be spaced apart from each other between the sidewall of the channel hole and the two or more channel patterns, respectively.

Abstract: A semiconductor device includes a first gate structure including a plurality of first conductive layers and a plurality of first insulating layers that are alternately stacked; an isolation insulating layer located in the first gate structure, the isolation insulating layer including a first line portion extending in a first direction, a plurality of first protrusions protruding from the first line portion towards one side of the first line portion in a second direction, and a plurality of second protrusions protruding from the first line portion towards another side of the first line portion in an opposite direction to the first protrusions, wherein the second direction is orthogonal to the first direction; a plurality of first memory patterns, wherein one of the plurality of first memory patterns surrounds one of the plurality of first protrusions; and a plurality of first passivation patterns, wherein one of the plurality of first passivation patterns is located between the first line portion and one of th

Abstract: A semiconductor device according to an embodiment of the present disclosure includes a first cell area and a second cell area adjacent to each other in a first direction, a support disposed between the first cell area and the second cell area, first gate lines stacked in the first cell area, first pads configured to extend from the first gate lines and configured to protrude upward along a first sidewall of the support, second gate lines stacked in the second cell area, second pads configured to extend from the second gate lines and configured to protrude upward along a second sidewall of the support, and first connection pads configured to extend in the first direction along a third sidewall of the support and configured to electrically connect the first pads with the second pads.

Abstract: The present disclosure includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stack including a plurality of conductive layers stacked to be spaced apart in a first direction, an opening in the stack extending in the first direction and having an elliptical shape in a plan view, and a first channel pattern and a second channel pattern spaced apart from each other in a second direction toward which a major axis of the elliptical shape faces in the opening, the first channel pattern and the second channel pattern extending in the first direction. Each of the first channel pattern and the second channel pattern includes a central portion overlapping with the major axis of the elliptical shape and bent portions extending away from the central portion.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device including a stacked body including conductive patterns and insulating patterns that are alternately stacked, a filling layer configured to pass through the stacked body, a first channel layer configured to pass through the stacked body and coupled to the filling layer, a second channel layer configured to pass through the stacked body and coupled to the filling layer, a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer, a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer, and a memory layer surrounding the filling layer, the first and second channel layers, and the first and second interposed layers.

Abstract: A semiconductor device including: a gate structure including stacked gate lines; an insulating core located in the gate structure and including a first long axis and a first short axis; a memory layer surrounding the insulating core; first channel pattern and a second channel pattern located facing each other along the first long axis, wherein the first channel pattern and the second channel pattern are located between the insulating core and the memory layer; and a capping layer located between the first channel pattern and the second channel pattern.

Abstract: There may be provided a method of manufacturing a semiconductor chip. A layer stack in which first material layers and second material layers are alternately stacked is formed on a semiconductor substrate that includes a chip region and a scribe lane region, and crack propagation guides are formed in a first portion of the layer stack within the scribe lane region.