Patents by Inventor Jung Gun Heo
Jung Gun Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150179434Abstract: A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (BCP) layer formed over the separation wall layer and filling gaps between the pillars. The BCP layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains.Type: ApplicationFiled: January 12, 2015Publication date: June 25, 2015Inventors: Keun Do BAN, Jung Gun HEO, Cheol Kyu BOK, Myoung Soo KIM
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Publication number: 20150155180Abstract: Various embodiments are directed to fine pattern structures, such as fine pattern structures having block co-polymer materials, methods of forming fine pattern structures with block co-polymer materials, and methods of fabricating semiconductor devices including fine pattern structures with block co-polymer materials. According to some embodiments, a method of fabricating a fine pattern structure includes providing a layer of alternating protrusion portions and recess portions, forming polymer patterns in recess regions formed in the recess portions, forming brush patterns on top surfaces of the protrusion portions, forming first polymer block patterns on the brush patterns and second polymer block patterns on the polymer patterns, and removing the second polymer block patterns and the polymer patterns.Type: ApplicationFiled: April 7, 2014Publication date: June 4, 2015Applicant: SK HYNIX INC.Inventors: Keun Do BAN, Cheol Kyu BOK, Myoung Soo KIM, Jung Gun HEO
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Patent number: 8962491Abstract: The method includes forming an array of first separation walls on an underlying layer. A block co-polymer (BCP) layer is formed to fill inside regions of the first separation walls and gaps between the first separation walls. The BCP layer is phase-separated to include first domains that provide second separation walls covering inner sidewalls and outer sidewalls of the first separation walls and second domains that are separated from each other by the first domains.Type: GrantFiled: December 23, 2013Date of Patent: February 24, 2015Assignee: SK Hynix Inc.Inventors: Keun Do Ban, Jung Gun Heo, Cheol Kyu Bok, Myoung Soo Kim
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Publication number: 20150031185Abstract: The method includes forming an array of first separation walls on an underlying layer. A block co-polymer (BCP) layer is formed to fill inside regions of the first separation walls and gaps between the first separation walls. The BCP layer is phase-separated to include first domains that provide second separation walls covering inner sidewalls and outer sidewalls of the first separation walls and second domains that are separated from each other by the first domains.Type: ApplicationFiled: December 23, 2013Publication date: January 29, 2015Applicant: SK HYNIX INC.Inventors: Keun Do BAN, Jung Gun HEO, Cheol Kyu BOK, Myoung Soo KIM
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Publication number: 20140206194Abstract: A method for manufacturing a semiconductor device includes forming an etch-target layer over a semiconductor substrate having a lower structure, forming a first mask pattern over the etch-target layer, forming a spacer material layer with a uniform thickness over the etch-target layer including the first mask pattern, forming a second mask pattern on an indented region of the space material layer, and etching the etch-target layer with the first mask pattern and the second mask pattern as an etch mask to form a fine pattern.Type: ApplicationFiled: March 25, 2014Publication date: July 24, 2014Applicant: SK hynix Inc.Inventors: Ki Lyoung Lee, Cheol Kyu Bok, Keun Do Ban, Jung Gun Heo
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Patent number: 8685627Abstract: A method for manufacturing a semiconductor device includes forming an etch-target layer over a semiconductor substrate having a lower structure, forming a first mask pattern over the etch-target layer, forming a spacer material layer with a uniform thickness over the etch-target layer including the first mask pattern, forming a second mask pattern on an indented region of the space material layer, and etching the etch-target layer with the first mask pattern and the second mask pattern as an etch mask to form a fine pattern.Type: GrantFiled: November 6, 2008Date of Patent: April 1, 2014Assignee: Hynix Semiconductor Inc.Inventors: Ki Lyoung Lee, Cheol Kyu Bok, Keum Do Ban, Jung Gun Heo
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Patent number: 7994050Abstract: A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the silicon resin comprises about 20 to 45% silicon molecules by weight, based on a total weight of the resin; forming a deposition structure by sequentially forming a self-arrangement contact (SAC) insulating film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; coating the multi-functional hard mask composition over the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film using a photoresist pattern as an etching mask, thereby forming a trench having a width greater than that of the via hole.Type: GrantFiled: July 15, 2010Date of Patent: August 9, 2011Assignee: Hynix Semiconductor Inc.Inventors: Ki Lyoung Lee, Jung Gun Heo
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Patent number: 7964510Abstract: A method for forming a pattern of a semiconductor device includes: forming a first mask film and a second mask film over an underlying layer; partially etching the first and second mask films using a photoresist mask pattern as an etching mask to form a intermediate mask pattern having a protrusion shape and including first and second mask film layers, over a remaining portion of the first mask film; forming a first spacer at sidewalls of the intermediate mask pattern etching the remaining portion of the first mask film and the first mask film layer of the intermediate mask pattern using the first spacer and the second mask film layer of the intermediate mask pattern as an etching mask to expose the underlying layer and form a mask pattern having first and second mask film layers; forming a second spacer at sidewalls of the mask pattern; and removing the mask pattern to form a symmetrical spacer pattern.Type: GrantFiled: December 29, 2008Date of Patent: June 21, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jung Gun Heo
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Publication number: 20100311239Abstract: A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the silicon resin comprises about 20 to 45% silicon molecules by weight, based on a total weight of the resin; forming a deposition structure by sequentially forming a self-arrangement contact (SAC) insulating film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; coating the multi-functional hard mask composition over the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film using a photoresist pattern as an etching mask, thereby forming a trench having a width greater than that of the via hole.Type: ApplicationFiled: July 15, 2010Publication date: December 9, 2010Inventors: Ki Lyoung Lee, Jung Gun Heo
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Patent number: 7811929Abstract: A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin; forming a deposition structure including a self-arrangement contact insulation film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; forming the multi-functional hard mask composition on the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film, thereby forming a trench having a width wider than that of the via hole; and removing the multi-functional hard mask film.Type: GrantFiled: June 22, 2007Date of Patent: October 12, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Ki Lyoung Lee, Jung Gun Heo
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Publication number: 20090246961Abstract: A method for forming a pattern of a semiconductor device includes: forming a first mask film and a second mask film over an underlying layer; partially etching the first and second mask films using a photoresist mask pattern as an etching mask to form a intermediate mask pattern having a protrusion shape and including first and second mask film layers, over a remaining portion of the first mask film; forming a first spacer at sidewalls of the intermediate mask pattern etching the remaining portion of the first mask film and the first mask film layer of the intermediate mask pattern using the first spacer and the second mask film layer of the intermediate mask pattern as an etching mask to expose the underlying layer and form a mask pattern having first and second mask film layers; forming a second spacer at sidewalls of the mask pattern; and removing the mask pattern to form a symmetrical spacer pattern.Type: ApplicationFiled: December 29, 2008Publication date: October 1, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jung Gun Heo
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Publication number: 20090162795Abstract: A method for manufacturing a semiconductor device includes forming an etch-target layer over a semiconductor substrate having a lower structure, forming a first mask pattern over the etch-target layer, forming a spacer material layer with a uniform thickness over the etch-target layer including the first mask pattern, forming a second mask pattern on an indented region of the space material layer, and etching the etch-target layer with the first mask pattern and the second mask pattern as an etch mask to form a fine pattern.Type: ApplicationFiled: November 6, 2008Publication date: June 25, 2009Applicant: Hynix Semiconductor Inc.Inventors: Ki Lyoung LEE, Cheol Kyu BOK, Keun Do BAN, Jung Gun HEO
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Publication number: 20080268641Abstract: A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin; forming a deposition. structure including a self-arrangement contact insulation film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; forming the multi-functional hard mask composition on the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film, thereby forming a trench having a width wider than that of the via hole; and removing the multi-functional hard mask film.Type: ApplicationFiled: June 22, 2007Publication date: October 30, 2008Inventors: Ki Lyoung Lee, Jung Gun Heo