Patents by Inventor Jung-Hao CHANG

Jung-Hao CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11121037
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Wei Tsai, Yu-Xuan Huang, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao, Jung-Hung Chang, Lo-Heng Chang, Pei-Hsun Wang, Kuo-Cheng Chiang
  • Patent number: 11114405
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure; a first conductive layer on the first transition layer; and a second conductive layer over the first conductive layer. The first conductive layer is substantially made of twinned copper. A first average roughness of a first top surface of the second conductive layer is less than a second average roughness of a second top surface of the first conductive layer.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Hua Chang, Po-Hao Tsai, Jing-Cheng Lin
  • Publication number: 20210273098
    Abstract: A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: Jung-Hung Chang, Lo-Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11107907
    Abstract: A method for manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor fin; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor fin; forming a gate structure on the semiconductor fin and between the gate spacers, wherein the gate structure comprises a gate dielectric layer and a work function metal over the gate dielectric layer; performing a first plasma etching process by using a first reactant to etch back the gate structure performing a second plasma etching process by using a second reactant on the etched-back gate structure, wherein the first plasma etching process has a first removal rate of the gate dielectric layer, the second plasma etching process has a second removal rate of the gate dielectric layer, and the second removal rate is greater than the first removal rate.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Hao Chang, Li-Te Lin
  • Publication number: 20210226057
    Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hung CHU, Sung-Li WANG, Fang-Wei LEE, Jung-Hao CHANG, Mrunal Abhijith KHADERBAD, Keng-Chu LIN
  • Publication number: 20210210614
    Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 8, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen LO, Jung-Hao CHANG, Li-Te LIN, Pinyen LIN
  • Patent number: 11011413
    Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Jung-Hao Chang, Chia-Hung Chu, Keng-Chu Lin
  • Patent number: 10957779
    Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Lo, Jung-Hao Chang, Li-Te Lin, Pinyen Lin
  • Publication number: 20200381535
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements and forming a metal gate stack in the recess. The method further includes etching back the metal gate stack while the metal gate stack is kept at a temperature that is in a range from about 20 degrees C. to about 55 degrees C. In addition, the method includes forming a protection element over the metal gate stack after etching back the metal gate stack.
    Type: Application
    Filed: November 6, 2019
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Hao Chang, Li-Te Lin, Pinyen Lin
  • Publication number: 20200287047
    Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Hao KUO, Jung-Hao CHANG, Chao-Hsien HUANG, Li-Te LIN, Kuo-Cheng CHING
  • Patent number: 10755943
    Abstract: A method includes forming a mandrel structure over a semiconductor substrate. A first spacer and a second spacer are formed alongside the mandrel structure. A mask layer is over a first portion of the first spacer, in which a second portion of the first spacer and the second spacer are exposed from the mask layer. The exposed second spacer is etched, in which etching the exposed second spacer is performed such that a polymer is formed over a top surface of the exposed second portion of the first spacer. The mask layer, the polymer, and the mandrel structure are removed. The semiconductor substrate is patterned using the first spacer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Hao Chang, Chao-Hsien Huang, Wen-Ting Lan, Shi-Ning Ju, Li-Te Lin, Kuo-Cheng Ching
  • Patent number: 10737932
    Abstract: A MEMS structure includes a substrate, a dielectric layer, a membrane, a backplate, and a blocking layer. The substrate has a through-hole. The dielectric layer is disposed on the substrate and has a cavity in communication with the through-hole. The membrane has at least one vent hole, is embedded in the dielectric layer and together with the dielectric layer defines a first chamber that communicates with the through-hole. The backplate is disposed on the dielectric layer. One end of the blocking layer is embedded in the dielectric layer, and the other end of the blocking layer extends into the cavity; the blocking layer is spatially isolated from the membrane and at least partially overlaps with the at least one vent hole.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 11, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yuan-Sheng Lin, Jung-Hao Chang, Chang-Sheng Hsu, Weng-Yi Chen
  • Publication number: 20200223687
    Abstract: A MEMS structure includes a substrate, a dielectric layer, a membrane, a backplate, and a blocking layer. The substrate has a through-hole. The dielectric layer is disposed on the substrate and has a cavity in communication with the through-hole. The membrane has at least one vent hole, is embedded in the dielectric layer and together with the dielectric layer defines a first chamber that communicates with the through-hole. The backplate is disposed on the dielectric layer. One end of the blocking layer is embedded in the dielectric layer, and the other end of the blocking layer extends into the cavity; the blocking layer is spatially isolated from the membrane and at least partially overlaps with the at least one vent hole.
    Type: Application
    Filed: February 25, 2019
    Publication date: July 16, 2020
    Inventors: Yuan-Sheng LIN, Jung-Hao CHANG, Chang-Sheng HSU, Weng-Yi CHEN
  • Patent number: 10680109
    Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Hao Kuo, Jung-Hao Chang, Chao-Hsien Huang, Li-Te Lin, Kuo-Cheng Ching
  • Publication number: 20200135901
    Abstract: A method for manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor fin; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor fin; forming a gate structure on the semiconductor fin and between the gate spacers, wherein the gate structure comprises a gate dielectric layer and a work function metal over the gate dielectric layer; performing a first plasma etching process by using a first reactant to etch back the gate structure performing a second plasma etching process by using a second reactant on the etched-back gate structure, wherein the first plasma etching process has a first removal rate of the gate dielectric layer, the second plasma etching process has a second removal rate of the gate dielectric layer, and the second removal rate is greater than the first removal rate.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Hao CHANG, Li-Te LIN
  • Publication number: 20190214296
    Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Jung-Hao Chang, Chia-Hung Chu, Keng-Chu Lin
  • Publication number: 20190165123
    Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.
    Type: Application
    Filed: October 11, 2018
    Publication date: May 30, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen LO, Jung-Hao CHANG, Li-Te LIN, Pinyen LIN
  • Publication number: 20190139777
    Abstract: A method includes forming a mandrel structure over a semiconductor substrate. A first spacer and a second spacer are formed alongside the mandrel structure. A mask layer is over a first portion of the first spacer, in which a second portion of the first spacer and the second spacer are exposed from the mask layer. The exposed second spacer is etched, in which etching the exposed second spacer is performed such that a polymer is formed over a top surface of the exposed second portion of the first spacer. The mask layer, the polymer, and the mandrel structure are removed. The semiconductor substrate is patterned using the first spacer.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Jung-Hao CHANG, Chao-Hsien HUANG, Wen-Ting LAN, Shi-Ning JU, Li-Te LIN, Kuo-Cheng CHING
  • Publication number: 20190097056
    Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 28, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Hao KUO, Jung-Hao CHANG, Chao-Hsien HUANG, Li-Te LIN, Kuo-Cheng CHING
  • Patent number: 10157751
    Abstract: A method for manufacturing a semiconductor device, including forming a first hard mask strip, a second hard mask strip, and a dummy structure over a substrate, in which the dummy structure is formed between and in contact with the first hard mask strip and the second hard mask strip; forming a hard mask layer over the first hard mask strip, the dummy structure, and the second hard mask strip; patterning the hard mask layer to form an opening exposing the first hard mask strip and the dummy structure, and partially exposing the second hard mask strip; and performing an etching process to remove the first hard mask strip and form a recess in the second hard mask strip, in which the performing the etching process includes forming a polymer in the recess.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Hao Chang, Chao-Hsien Huang, Wen-Ting Lan, Shi-Ning Ju, Li-Te Lin, Kuo-Cheng Ching