Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

Abstract: A plate cooling device for cooling carrier plate of a wafer, includes a cooling plate and a plurality of contact pads. The cooling plate includes an upper surface; wherein the upper surface is provided with a cooling area for placing the wafer thereon. The contact pads are disposed on the upper surface. The contact pads protrude on the upper surface, and the total area of the contact pads is less than 3% of the area of the carrier plate.

Abstract: A method is provided. The method includes: receiving a semiconductor structure having a first material and a second material; performing a first etch on the first material for a first duration under a first etching chemistry; and performing a second etch on the second material for a second duration under a second etching chemistry, wherein the first material includes a first incubation time and the second material includes a second incubation time greater than the first incubation time under the first etching chemistry. The first material includes a third incubation time and the second material includes a fourth incubation time less than the third incubation time under the second etching chemistry.

Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a first transistor. The first transistor includes a first gate structure wrapping around a plurality of first nanostructures disposed over a substrate, a first source/drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer, and a first semiconductor layer disposed between the substrate and the first source/drain feature, wherein the first source/drain feature is in direct contact with a top surface of the first semiconductor layer.

Abstract: A low concentration ozone gas supply device includes an ozone dilution tank, an ozone generator, a dilution gas supplier, and plural gas reservoir. The ozone dilution tank is provided with a dilution space, and the ozone dilution tank is provided with an overflow vent connected to the dilution space. The ozone generator is configured to continuously supply ozone to the dilution space of the ozone dilution tank. The dilution gas supplier is configured to supply a dilution gas to the dilution space, so that the ozone is mixed with the dilution gas in the dilution space to form the low concentration ozone gas, and the low concentration ozone gas in the dilution space continuously overflows via the overflow vent. The gas reservoirs are connected to the dilution space; wherein the volume of the dilution space is larger than the sum of the volumes of gas reservoirs.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.

Abstract: A device includes: a substrate; a stack of semiconductor channels on the substrate; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; and a hybrid structure between the source/drain region and the substrate. The hybrid structure includes: a first semiconductor layer under the source/drain region; and an isolation region extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer.

Abstract: A semiconductor device structure includes a substrate and a metal gate stack over the substrate. The metal gate stack has a gate dielectric layer and a work function layer over the gate dielectric layer, and the gate dielectric layer has a curved sidewall and a vertical sidewall. The semiconductor device structure also includes a protection element over the metal gate stack, and the protection element extends conformally along the curved sidewall and the vertical sidewall to reach a topmost surface of the work function layer. The semiconductor device structure further includes a spacer structure over a sidewall of the metal gate stack. A topmost surface of the gate dielectric layer is lower than a topmost surface of the spacer structure, and the topmost surface of the gate dielectric layer is closer to the topmost surface of the spacer structure than the topmost surface of the work function layer.

Abstract: A UV-assisted and plasma-enhanced process method includes: providing a lower chamber and a reaction space defined therein; providing an upper cover, wherein the upper cover has a window and vent holes; sealing a chamber opening of the lower chamber with the upper cover to form a reaction chamber; providing an outer tube body and an inner tube body disposed in the outer tube body, the outer tube body covering the window and the vent holes, and the inner tube body connected to the window; providing a UV light source at a top end of the inner tube body; providing an induction coil around the outer tube body; inducing a first gas to a first gas chamber in the inner tube body and a second gas to the second gas chamber between the inner and outer tube bodies; and activating the UV light source and the induction coil optionally.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.

Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.

Abstract: A semiconductor device that has two transistors and a source/drain contact. The first transistor has a layer of semiconductor material that acts as a channel, a structure that serves as a gate and wraps around the semiconductor channel layer, and two epitaxy structures on either end of the semiconductor channel layer that function as the source and drain. The second transistor is situated above the first transistor and has similar components, including a semiconductor channel layer, gate structure, and source/drain epitaxy structures. The connection between the first and second source/drain epitaxy structures is made by a source/drain contact that passes through one of the second source/drain epitaxy structures. This contact is made up of a metal plug and a metal liner that lines the plug.

Abstract: A micro electromechanical system (MEMS) includes a substrate and a rear surface opposite to the surface, a semiconductor device and a protection wall. The substrate has a surface. The semiconductor device is disposed on the surface. The protection wall surrounds the semiconductor device and passes through the surface but not electrically contacts to the semiconductor device; wherein there is no electronic element disposed between the surface and the rear surface.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a metal gate stack over the substrate. The metal gate stack has a gate dielectric layer and a work function layer over the gate dielectric layer. The semiconductor device structure also includes a spacer structure over a sidewall of the metal gate stack. A topmost surface of the gate dielectric layer is lower than a topmost surface of the spacer structure. The topmost surface of the gate dielectric layer is closer to the topmost surface of the spacer structure than a topmost surface of the work function layer.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.

Abstract: The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber and an ion source in the chamber. The ion source can include an outlet. The ion source can be configured to generate a particle beam. The semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. A first portion of the grid structure can be electrically insulated from a second portion of the grid structure.

Abstract: A micro electromechanical system (MEMS) includes a substrate, a semiconductor device and a protection wall. The substrate has a surface. The semiconductor device is disposed on the surface. The protection wall has a poly-silicon layer surrounding the semiconductor device and connecting to the surface.

Abstract: A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

Abstract: The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber and an ion source in the chamber. The ion source can include an outlet. The ion source can be configured to generate a particle beam. The semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. A first portion of the grid structure can be electrically insulated from a second portion of the grid structure.