Patents by Inventor Jung-Hao CHANG
Jung-Hao CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11107907Abstract: A method for manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor fin; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor fin; forming a gate structure on the semiconductor fin and between the gate spacers, wherein the gate structure comprises a gate dielectric layer and a work function metal over the gate dielectric layer; performing a first plasma etching process by using a first reactant to etch back the gate structure performing a second plasma etching process by using a second reactant on the etched-back gate structure, wherein the first plasma etching process has a first removal rate of the gate dielectric layer, the second plasma etching process has a second removal rate of the gate dielectric layer, and the second removal rate is greater than the first removal rate.Type: GrantFiled: October 3, 2019Date of Patent: August 31, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Hao Chang, Li-Te Lin
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Publication number: 20210226057Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.Type: ApplicationFiled: January 16, 2020Publication date: July 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hung CHU, Sung-Li WANG, Fang-Wei LEE, Jung-Hao CHANG, Mrunal Abhijith KHADERBAD, Keng-Chu LIN
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Publication number: 20210210614Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.Type: ApplicationFiled: March 19, 2021Publication date: July 8, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen LO, Jung-Hao CHANG, Li-Te LIN, Pinyen LIN
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Patent number: 11011413Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.Type: GrantFiled: March 15, 2019Date of Patent: May 18, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Shuen-Shin Liang, Jung-Hao Chang, Chia-Hung Chu, Keng-Chu Lin
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Patent number: 10957779Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.Type: GrantFiled: October 11, 2018Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen Lo, Jung-Hao Chang, Li-Te Lin, Pinyen Lin
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Publication number: 20200381535Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements and forming a metal gate stack in the recess. The method further includes etching back the metal gate stack while the metal gate stack is kept at a temperature that is in a range from about 20 degrees C. to about 55 degrees C. In addition, the method includes forming a protection element over the metal gate stack after etching back the metal gate stack.Type: ApplicationFiled: November 6, 2019Publication date: December 3, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jung-Hao Chang, Li-Te Lin, Pinyen Lin
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Publication number: 20200287047Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.Type: ApplicationFiled: May 21, 2020Publication date: September 10, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Hao KUO, Jung-Hao CHANG, Chao-Hsien HUANG, Li-Te LIN, Kuo-Cheng CHING
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Patent number: 10755943Abstract: A method includes forming a mandrel structure over a semiconductor substrate. A first spacer and a second spacer are formed alongside the mandrel structure. A mask layer is over a first portion of the first spacer, in which a second portion of the first spacer and the second spacer are exposed from the mask layer. The exposed second spacer is etched, in which etching the exposed second spacer is performed such that a polymer is formed over a top surface of the exposed second portion of the first spacer. The mask layer, the polymer, and the mandrel structure are removed. The semiconductor substrate is patterned using the first spacer.Type: GrantFiled: December 17, 2018Date of Patent: August 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Hao Chang, Chao-Hsien Huang, Wen-Ting Lan, Shi-Ning Ju, Li-Te Lin, Kuo-Cheng Ching
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Patent number: 10737932Abstract: A MEMS structure includes a substrate, a dielectric layer, a membrane, a backplate, and a blocking layer. The substrate has a through-hole. The dielectric layer is disposed on the substrate and has a cavity in communication with the through-hole. The membrane has at least one vent hole, is embedded in the dielectric layer and together with the dielectric layer defines a first chamber that communicates with the through-hole. The backplate is disposed on the dielectric layer. One end of the blocking layer is embedded in the dielectric layer, and the other end of the blocking layer extends into the cavity; the blocking layer is spatially isolated from the membrane and at least partially overlaps with the at least one vent hole.Type: GrantFiled: February 25, 2019Date of Patent: August 11, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yuan-Sheng Lin, Jung-Hao Chang, Chang-Sheng Hsu, Weng-Yi Chen
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Publication number: 20200223687Abstract: A MEMS structure includes a substrate, a dielectric layer, a membrane, a backplate, and a blocking layer. The substrate has a through-hole. The dielectric layer is disposed on the substrate and has a cavity in communication with the through-hole. The membrane has at least one vent hole, is embedded in the dielectric layer and together with the dielectric layer defines a first chamber that communicates with the through-hole. The backplate is disposed on the dielectric layer. One end of the blocking layer is embedded in the dielectric layer, and the other end of the blocking layer extends into the cavity; the blocking layer is spatially isolated from the membrane and at least partially overlaps with the at least one vent hole.Type: ApplicationFiled: February 25, 2019Publication date: July 16, 2020Inventors: Yuan-Sheng LIN, Jung-Hao CHANG, Chang-Sheng HSU, Weng-Yi CHEN
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Patent number: 10680109Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.Type: GrantFiled: September 25, 2018Date of Patent: June 9, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Hao Kuo, Jung-Hao Chang, Chao-Hsien Huang, Li-Te Lin, Kuo-Cheng Ching
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Publication number: 20200135901Abstract: A method for manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor fin; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor fin; forming a gate structure on the semiconductor fin and between the gate spacers, wherein the gate structure comprises a gate dielectric layer and a work function metal over the gate dielectric layer; performing a first plasma etching process by using a first reactant to etch back the gate structure performing a second plasma etching process by using a second reactant on the etched-back gate structure, wherein the first plasma etching process has a first removal rate of the gate dielectric layer, the second plasma etching process has a second removal rate of the gate dielectric layer, and the second removal rate is greater than the first removal rate.Type: ApplicationFiled: October 3, 2019Publication date: April 30, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Hao CHANG, Li-Te LIN
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Publication number: 20190214296Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.Type: ApplicationFiled: March 15, 2019Publication date: July 11, 2019Inventors: Sung-Li Wang, Shuen-Shin Liang, Jung-Hao Chang, Chia-Hung Chu, Keng-Chu Lin
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Publication number: 20190165123Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.Type: ApplicationFiled: October 11, 2018Publication date: May 30, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen LO, Jung-Hao CHANG, Li-Te LIN, Pinyen LIN
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Publication number: 20190139777Abstract: A method includes forming a mandrel structure over a semiconductor substrate. A first spacer and a second spacer are formed alongside the mandrel structure. A mask layer is over a first portion of the first spacer, in which a second portion of the first spacer and the second spacer are exposed from the mask layer. The exposed second spacer is etched, in which etching the exposed second spacer is performed such that a polymer is formed over a top surface of the exposed second portion of the first spacer. The mask layer, the polymer, and the mandrel structure are removed. The semiconductor substrate is patterned using the first spacer.Type: ApplicationFiled: December 17, 2018Publication date: May 9, 2019Inventors: Jung-Hao CHANG, Chao-Hsien HUANG, Wen-Ting LAN, Shi-Ning JU, Li-Te LIN, Kuo-Cheng CHING
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Publication number: 20190097056Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.Type: ApplicationFiled: September 25, 2018Publication date: March 28, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Hao KUO, Jung-Hao CHANG, Chao-Hsien HUANG, Li-Te LIN, Kuo-Cheng CHING
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Patent number: 10157751Abstract: A method for manufacturing a semiconductor device, including forming a first hard mask strip, a second hard mask strip, and a dummy structure over a substrate, in which the dummy structure is formed between and in contact with the first hard mask strip and the second hard mask strip; forming a hard mask layer over the first hard mask strip, the dummy structure, and the second hard mask strip; patterning the hard mask layer to form an opening exposing the first hard mask strip and the dummy structure, and partially exposing the second hard mask strip; and performing an etching process to remove the first hard mask strip and form a recess in the second hard mask strip, in which the performing the etching process includes forming a polymer in the recess.Type: GrantFiled: October 26, 2017Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Hao Chang, Chao-Hsien Huang, Wen-Ting Lan, Shi-Ning Ju, Li-Te Lin, Kuo-Cheng Ching
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Publication number: 20150060119Abstract: A conductive structure comprises a plurality of first nanowires and a plurality of second nanowires. The first nanowires extend along a first direction substantially. The second nanowires extend along a second direction substantially, and at least a part of the second nanowires electrical connect to the first nanowires. The included angle between the first and second directions is nonzero. A manufacturing method of the conductive structure is also disclosed.Type: ApplicationFiled: November 27, 2013Publication date: March 5, 2015Applicant: National Tsing Hua UniversityInventors: Hao-Wu LIN, Kai-Ming CHIANG, Jung-Hao CHANG, Cheng-Yu HUANG, Chih-Wei LU