Abstract: Disclosed is a method of manufacturing an epitaxy oxide thin film of enhanced crystalline quality, and an epitaxy oxide thin film manufactured thereby according to the present invention. With respect to the manufacturing method of the epitaxy oxide thin film, which epitaxially grows an orientation film with an oxide capable of being oriented to (001), (110), and (111) on a single crystal Si substrate, because time required for raising a temperature of the orientation film up to an annealing temperature at room temperature is extremely minimized, thermal stress arising from the large difference in thermal expansion coefficients between the substrate and the orientation film is controlled, so crystalline quality of the epitaxy oxide thin film can be enhanced. Moreover, various epitaxial functional oxides are integrated into the thin film of enhanced crystalline quality so that a novel electronic device can be embodied.

Abstract: Provided is an apparatus for generating direct current using continuous polarization change of piezoelectric materials. For example, a piezoelectric direct current generator includes a first electrode, a polarized piezoelectric material layer disposed on a first surface of the first electrode, and a second electrode disposed on a surface opposite to the first electrode and coupled to move along the piezoelectric material layer while pressing the piezoelectric material layer.

Abstract: The present invention pertains to a pharmaceutical composition for preventing or treating squamous cell carcinoma, the pharmaceutical composition containing a highly expressed lncRNAs in esophageal squamous cell carcinoma (HERES) expression inhibitor. More specifically, the present invention pertains to a pharmaceutical composition which uses a HERES expression inhibitor to reduce the expression of HERES and affect Wnt signaling pathways, and thereby prevent or treat squamous cell carcinoma. The present inventors discovered that the expression pattern of HERES is related to the onset of squamous cell carcinoma, and found that HERES can be a target for treating squamous cell carcinoma.

Abstract: Provided are a semiconductor technique, and more particularly, to a variable resistor, a non-volatile memory device using the same, and a method of fabricating the same. The variable resistor may include a first electrode including titanium (Ti); a second electrode for forming a Schottky barrier; and a stacked structure including an oxygen-deficient hafnium oxide film (HfO2-x, 0<x<2) between the first electrode and the second electrode, an oxygen-deficient titanium oxide (TiOx) film between the oxygen-deficient hafnium oxide film and the first electrode, and a stoichiometric tantalum oxide (Ta2O5) film between the oxygen-deficient hafnium oxide film and the second electrode.

Abstract: A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.

Abstract: An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

Abstract: There are provided a semiconductor package including an antenna formed integrally therewith, and a method of manufacturing the same. The semiconductor package includes: a semiconductor chip; a sealing part sealing the semiconductor chip; a substrate part formed on at least one surface of the sealing part; and an antenna part formed on the sealing part or the substrate part and electrically connected to the semiconductor chip.

Abstract: Provided are a semiconductor technique, and more particularly, to a variable resistor, a non-volatile memory device using the same, and a method of fabricating the same. The variable resistor may include a first electrode including titanium (Ti); a second electrode for forming a Schottky barrier; and a stacked structure including an oxygen-deficient hafnium oxide film (HfO2-x, 0<x<2) between the first electrode and the second electrode, an oxygen-deficient titanium oxide (TiOx) film between the oxygen-deficient hafnium oxide film and the first electrode, and a stoichiometric tantalum oxide (Ta2O5) film between the oxygen-deficient hafnium oxide film and the second electrode.

Abstract: An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

Abstract: Disclosed herein are a wireless power transmission apparatus and a transmission method thereof. The wireless power transmission apparatus is configured to include a wireless power transmitter generating a wireless power signal to be wireless transmitted, wirelessly transmitting the generated wireless power signal by a magnetic resonance manner, receiving a reflection wireless power signal to determine whether or not a load apparatus is presented, and supplying power to the load apparatus; and a wireless power receiver connected to the load apparatus and receiving the transmitted wireless power signal by the magnetic resonance manner and supplying it to the connected load apparatus and reflecting the remaining wireless power signal to the wireless power transmitter, whereby a transmission apparatus can recognize a receiving environment and resonance characteristics are improved, without a separate communication device or a system.

Abstract: A semiconductor package including an antenna formed integrally therewith. The semiconductor package includes: a semiconductor chip; a sealing part sealing the semiconductor chip; a substrate part formed on at least one surface of the sealing part; and an antenna part formed on the sealing part and electrically connected to the semiconductor chip.

Abstract: A current mirror circuit for biasing a power amplifier includes a modified Wilson current mirror with a pair of first and second mirror transistors connected to a third transistor. The first mirror transistor is configured for operating in a saturation mode, with a gate voltage of the first mirror transistor being lower than a gate voltage of the power amplifier. The third transistor charges the power amplifier circuit during a positive half cycle of an input signal and the first mirror transistor discharges the power amplifier circuit during a negative half cycle of the input signal at different rates.

Abstract: Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.

Abstract: A semiconductor package according to some examples may include a first portion of a support plate configured as an RF signal connection, a semiconductor die thermally coupled to a second portion of the support plate to dissipate heat, a first redistribution layer positioned in close proximity to a second redistribution layer to capacitively couple the first redistribution layer to the second redistribution layer, a first via extending between the first portion and the first redistribution layer, and a second via in close proximity to the first via to capacitively couple the second via to the first via.

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract: A semiconductor device package is provided with integrated antenna for wireless applications. The semiconductor device package comprises a substrate including a semiconductor chip mounted thereon: a protective layer covering the semiconductor chip; a metal pattern mounted on the protective layer; and a first connective member connecting the semiconductor chip and the metal pattern. According to this configuration, the semiconductor device package is capable of being easily manufactured while minimizing the electrical distance between the metal pattern for use as an antenna and the semiconductor chip.

Abstract: Disclosed herein are a multi wireless charging apparatus and a method for manufacturing the same. The multi wireless charging apparatus includes: a control unit wholly controlling a multi wireless charging process; and a plurality of wireless charging units electrically connected with the control and deformed into a roll form by being bonded so as to a plurality of interlayer voids at the time of laminating a plurality of flexible substrates. By this configuration, the multi wireless charging apparatus can be rolled up in a roll form while having a slim thickness and therefore, can be conveniently carried.

Abstract: A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.

Abstract: A semiconductor device package is provided with integrated antenna for wireless applications. The semiconductor device package comprises a substrate including a semiconductor chip mounted thereon; a protective layer covering the semiconductor chip; a metal pattern mounted on the protective layer; and a first connective member connecting the semiconductor chip and the metal pattern. According to this configuration, the semiconductor device package is capable of being easily manufactured while minimizing the electrical distance between the metal pattern for use as an antenna and the semiconductor chip.

Abstract: A package substrate (or printed circuit board) that includes at least one dielectric layer, a first inductor structure is at least partially located in the dielectric layer, a third interconnect, and a second inductor structure. The first inductor structure includes a first interconnect, a first via coupled to the first interconnect, and a second interconnect coupled to the first via. The third interconnect is coupled to the first inductor structure. The third interconnect is configured to provide an electrical path for a ground signal. The second inductor structure is at least partially located in the dielectric layer. The second inductor is coupled to the third interconnect. The second inductor structure includes a fourth interconnect, a second via coupled to the fourth interconnect, and a fifth interconnect coupled to the second via. The first and second inductor structures are configured to operate with a capacitor as a 3rd harmonic suppression filter.