Patents by Inventor Jung-Hoon Chun
Jung-Hoon Chun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10483985Abstract: An oscillator using a supply regulation loop and a method of operating the oscillator are provided.Type: GrantFiled: December 7, 2017Date of Patent: November 19, 2019Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan UniversityInventors: Chisung Bae, Sangjoon Kim, Yoonmyung Lee, Jaehong Jung, Jung-Hoon Chun
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Publication number: 20190280848Abstract: A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.Type: ApplicationFiled: August 22, 2018Publication date: September 12, 2019Applicants: Samsung Electronics Co.,Ltd., Research & Business Foundation Sungkyunkwan UniversityInventors: Sung-Ha Kim, Hwa Seok Oh, Jin Hyeok Choi, Jung-Hoon Chun
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Publication number: 20190253044Abstract: A transmitter includes: a pulse amplitude modulation encoder that encodes serial data to multi-bit transmission data of a first data group and a second data group; a first driver that converts first multi-bit transmission data of the first data group to a first differential signal having a first voltage swing width; a second driver that converts second multi-bit transmission data of the second data group to a second differential signal having a second voltage swing width narrower than the first voltage swing width; a first voltage regulator that provides to the second driver a first low swing voltage for generating the second differential signal; a second voltage regulator that provides to the second driver a second low swing voltage less than the first low swing voltage; and a constant current load switch that provides a current path between the first and second voltage regulators depending on deactivation of the second driver.Type: ApplicationFiled: April 24, 2019Publication date: August 15, 2019Inventors: SUNG-HA KIM, JUNG HOON CHUN, HWASEOK OH
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Patent number: 10312896Abstract: A transmitter includes: a pulse amplitude modulation encoder that encodes serial data to multi-bit transmission data of a first data group and a second data group; a first driver that converts first multi-bit transmission data of the first data group to a first differential signal having a first voltage swing width; a second driver that converts second multi-bit transmission data of the second data group to a second differential signal having a second voltage swing width narrower than the first voltage swing width; a first voltage regulator that provides to the second driver a first low swing voltage for generating the second differential signal; a second voltage regulator that provides to the second driver a second low swing voltage less than the first low swing voltage; and a constant current load switch that provides a current path between the first and second voltage regulators depending on deactivation of the second driver.Type: GrantFiled: March 19, 2018Date of Patent: June 4, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Ha Kim, Jung Hoon Chun, Hwaseok Oh
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Publication number: 20190044768Abstract: A transmitter includes: a pulse amplitude modulation encoder that encodes serial data to multi-bit transmission data of a first data group and a second data group; a first driver that converts first multi-bit transmission data of the first data group to a first differential signal having a first voltage swing width; a second driver that converts second multi-bit transmission data of the second data group to a second differential signal having a second voltage swing width narrower than the first voltage swing width; a first voltage regulator that provides to the second driver a first low swing voltage for generating the second differential signal; a second voltage regulator that provides to the second driver a second low swing voltage less than the first low swing voltage; and a constant current load switch that provides a current path between the first and second voltage regulators depending on deactivation of the second driver.Type: ApplicationFiled: March 19, 2018Publication date: February 7, 2019Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITYInventors: SUNG-HA KIM, JUNG HOON CHUN, HWASEOK OH
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Publication number: 20180359060Abstract: A serial communication interface circuit includes a transmitter configured to convert first parallel data into first serial data and transmit the first serial data through an output port; a receiver configured to receive second serial data through an input port and convert the second serial data into second parallel data; a test controller configured to generate at least one test control signal; and an embedded external loopback circuit configured to form an external loopback path between the output port and the input port to receive the first serial data and output the second serial data according to at least one channel model in response to the at least one test control signal in a test mode.Type: ApplicationFiled: January 10, 2018Publication date: December 13, 2018Applicants: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVER SITYInventors: SUNG-HA KIM, JUNG-HOON CHUN
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Publication number: 20180212610Abstract: An oscillator using a supply regulation loop and a method of operating the oscillator are provided.Type: ApplicationFiled: December 7, 2017Publication date: July 26, 2018Applicants: SAMSUNG ELECTRONICS CO., LTD., Research & Business Foundation SUNGKYUNKWAN UNIVER SITYInventors: Chisung Bae, Sangjoon Kim, Yoonmyung Lee, Jaehong Jung, Jung-Hoon Chun
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Publication number: 20170354609Abstract: The disclosure describes an injection molding process for coating a tablet core to produce a coated pharmaceutical tablet, wherein the injection-molded coating is substantially continuous (e.g., completely covers the tablet core with no openings), and describes the resulting coated pharmaceutical tablet. The disclosure describes compositions for coatings and tablet cores and equipment suitable for performing the process.Type: ApplicationFiled: June 12, 2017Publication date: December 14, 2017Applicant: Massachusetts Institute of TechnologyInventors: Vibha Puri, Parind Mahendrakumar Desai, Keith D. Jensen, David Brancazio, Eranda Harinath, Alexander Racine Martinez, Jung Hoon Chun, Richard Dean Braatz, Allan S. Myerson, Bernhardt Levy Trout
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Patent number: 9658643Abstract: A data interface includes a first sampler sampling a first bitset and a second sampler sampling a second bitset. The first bitset includes a first bit which is included in a first image data and a third bit which is included in a second image, and the second bitset includes a second bit which is included in the first image data and is a higher-order bit than the first bit and a fourth bit which is included in the second image data and is a higher-order bit than the third bit. The data interface further includes a clock generator configured to adjust a sampling timing of the first and second bitsets based on a multi-phase clock, and a clock data recovery (CDR) circuit shared by the first sampler, the second sampler and configured to output the multi-phase clock to the clock generator.Type: GrantFiled: February 16, 2015Date of Patent: May 23, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Kyun Jeong, Jung-Hoon Chun, June-Hee Lee, Won-Ho Choi
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Patent number: 9654118Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.Type: GrantFiled: June 10, 2016Date of Patent: May 16, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Junhan Bae, Kee-Won Kwon, Kyungho Kim, Jung Hoon Chun, Youngsoo Sohn, Seok Kim
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Patent number: 9491011Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.Type: GrantFiled: July 31, 2014Date of Patent: November 8, 2016Assignee: Rambus Inc.Inventors: Jaeha Kim, Haechang Lee, Jung-Hoon Chun, Jared Zerbe
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Publication number: 20160315625Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.Type: ApplicationFiled: June 10, 2016Publication date: October 27, 2016Applicant: Samsung Electronics Co., Ltd.Inventors: Junhan BAE, Kee-Won KWON, Kyungho KIM, Jung Hoon CHUN, Youngsoo SOHN, Seok KIM
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Patent number: 9385730Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.Type: GrantFiled: May 8, 2014Date of Patent: July 5, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Junhan Bae, Kee-won Kwon, Kyoungho Kim, Jung Hoon Chun, Youngsoo Sohn, Seok Kim
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Patent number: 9356772Abstract: A clock data recovery circuit includes a sampler to sample incoming data bits, a phase detector to generate an edge position signal and a polarity signal based on the sampled incoming data, a finite state machine to save a current edge position state, a polarity decision unit to generate a polarity inversion signal to invert the polarity signal, a gain controller to generate a tracking bandwidth signal, a recovery loop configured to adjust an edge offset of the reference clock, and a bit selector configured to recover the incoming data. The clock data recovery circuit has a first latency at a first operation mode and a second latency at a second operation mode. The phase detector in the clock data recovery circuit may include a first phase detector and a second detector combined together for a low latency and low lock time of the clock data recovery circuit.Type: GrantFiled: September 18, 2014Date of Patent: May 31, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hee Lee, Jongshin Shin, YoungKyun Jeong, Dongchul Choi, Jung-Hoon Chun
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Publication number: 20160116936Abstract: A data interface includes a first sampler sampling a first bitset and a second sampler sampling a second bitset. The first bitset includes a first bit which is included in a first image data and a third bit which is included in a second image, and the second bitset includes a second bit which is included in the first image data and is a higher-order bit than the first bit and a fourth bit which is included in the second image data and is a higher-order bit than the third bit. The data interface further includes a clock generator configured to adjust a sampling timing of the first and second bitsets based on a multi-phase clock, and a clock data recovery (CDR) circuit shared by the first sampler, the second sampler and configured to output the multi-phase clock to the clock generator.Type: ApplicationFiled: February 16, 2015Publication date: April 28, 2016Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITYInventors: YOUNG-KYUN JEONG, JUNG-HOON CHUN, JUNE-HEE LEE, WON-HO CHOI
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Patent number: 9205089Abstract: Layer processing for pharmaceuticals, and related systems, methods, and articles are generally described. In some embodiments, ingestible pharmaceutical products (e.g., tablets) can be formed by processing one or more layers containing a pharmaceutically active composition. For example, at least one layer containing a pharmaceutically active composition can be manipulated (e.g., folded, rolled, stacked, etc.) such that the average thickness of the product formed by the manipulation is at least about two times the average thickness of the portions of the layer(s) used to form the product. In some embodiments, after the layer is manipulated, it can be processed (e.g., cut, coated, etc.) to form a final product such as, for example, a tablet.Type: GrantFiled: April 27, 2012Date of Patent: December 8, 2015Assignee: Massachusetts Institute of TechnologyInventors: Bernhardt Levy Trout, Trevor Alan Hatton, Emily Chang, James M B Evans, Salvatore Mascia, Won Kim, Ryan Richard Slaughter, Yi Du, Himanshu Hemant Dhamankar, Keith M. Forward, Gregory C. Rutledge, Mao Wang, Allan Stuart Myerson, Blair Kathryn Brettmann, Nikhil Padhye, Jung-Hoon Chun
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Publication number: 20150207651Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.Type: ApplicationFiled: July 31, 2014Publication date: July 23, 2015Inventors: Jaeha Kim, Haechang Lee, Jung-Hoon Chun, Jared Zerbe
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Publication number: 20140333346Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.Type: ApplicationFiled: May 8, 2014Publication date: November 13, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Junhan BAE, Kee-won KWON, Kyoungho KIM, Jung Hoon CHUN, Youngsoo SOHN, Seok KIM
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Patent number: 8817849Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.Type: GrantFiled: March 25, 2008Date of Patent: August 26, 2014Assignee: Rambus Inc.Inventors: Jaeha Kim, Haechang Lee, Jung-Hoon Chun, Jared Zerbe
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Patent number: 8758091Abstract: Polishing pad conditioning system. The system includes a first rotatable platen supporting a polishing pad containing asperities having a radius of curvature. A second rotatable platen supports a disk of bulk material having holes therethrough, the second rotatable platen supported for translation as well as rotation. Means are provided for pushing the polishing pad and bulk material into contact at an interface during rotation and translation and means are provided for passing a slurry through the holes in the bulk material to the interface whereby the radius of curvature of the pad asperities is increased. Water may be delivered to the bulk material for cooling. A process for conditioning a polishing pad is also disclosed.Type: GrantFiled: April 6, 2010Date of Patent: June 24, 2014Assignee: Massachusetts Institute of TechnologyInventors: Nannaji Saka, Thor Eusner, Jung-Hoon Chun