Abstract: A circuit board comprises a mother substrate including first and second scribing regions, the first scribing region extending in first direction, the second scribing region extending in second direction, the first and second directions crossing each other, the mother substrate including chip regions defined by the first and second scribing regions, and a through via penetrating the chip regions of the mother substrate. The mother substrate comprises a first alignment pattern protruding from a top surface of the mother substrate. The first alignment pattern is disposed on at least one of the scribing regions.

Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

Abstract: A semiconductor chip is provided including an integrated circuit on a substrate; pads electrically connected to the integrated circuit; a lower insulating structure defining contact holes exposing the pads, respectively; and first, second and third conductive patterns electrically connected to the pads. The second conductive pattern is between the first conductive pattern and the third conductive pattern when viewed from a plan view. Each of the first to third conductive patterns includes a contact portion filling the contact hole, a first conductive line portion extending in one direction on the lower insulating structure, and a bonding pad portion. Ends of the bonding pad portions of the first and third conductive patterns protrude in the one direction as compared with an end of the bonding pad portion of the second conductive pattern when viewed from a plan view.

Abstract: A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same are provided. The semiconductor chip includes an integrated circuit on a substrate, a pad electrically connected to the integrated circuit, a lower insulating structure having a contact hole exposing the pad, and a conductive pattern including a contact portion filling the contact hole, a conductive line portion provided on the lower insulating structure to extend in a specific direction, and a bonding pad portion. The contact portion has a first thickness in a direction substantially perpendicular to a top surface of the substrate and a second thickness in another direction substantially parallel to the top surface of the substrate, the first thickness is greater than the second thickness, and the lower insulating structure includes a plurality of air gaps formed therein.

Abstract: A capacitor structure includes a plurality of lower electrodes, a support pattern structure, a dielectric layer, and an upper electrode. The lower electrodes are formed on a substrate. The support pattern structure is formed between the lower electrodes, and includes a lower support pattern and an upper support pattern structure over the lower support pattern. The upper support pattern structure includes a plurality of upper support patterns spaced apart from each other in a direction substantially perpendicular to a top surface of the substrate. The dielectric layer is formed on the lower electrodes and the support pattern structure. The upper electrode is formed on the dielectric layer. A sum of thicknesses of the plurality of upper support patterns in the direction substantially perpendicular to the top surface of the substrate is about 35% to about 85% of a total thickness of the upper support pattern structure.

Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.

Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.

Abstract: The present invention relates to a method for manufacturing an imine having no substituent group on the nitrogen by using, as a catalyst, a metal complex on an organic azide compound, and more specifically relates to a method in which a metal-complex catalyst is used to produce, from an organic azide having an alpha-hydrogen, an imine having no substituent group on the nitrogen via a continuous nitrogen removal and 1,2-hydrogen transfer reaction. The imine having no substituent group on the nitrogen manufactured by means of the method of the present invention can synthesize diverse coupling products comprising amine compounds by means of reactions with diverse nucleophiles.

Abstract: A semiconductor device includes a semiconductor structure having a first wire extending in a first direction, an intermetallic insulating layer covering the semiconductor structure, a via structure penetrating the intermetallic insulating layer, and a second wire extending on the intermetallic insulating layer in a second direction at a predetermined angle with respect to the first direction, the second wire being connected to the first wire through the via structure and including first and second portions on each other, and a protruding portion protruding from at least one of the first and second portions, the protruding portion being at a boundary of the first and second portions.

Abstract: The present invention relates to a method for manufacturing an imine having no substituent group on the nitrogen by using, as a catalyst, a metal complex on an organic azide compound, and more specifically relates to a method in which a metal-complex catalyst is used to produce, from an organic azide having an alpha-hydrogen, an imine having no substituent group on the nitrogen via a continuous nitrogen removal and 1,2-hydrogen transfer reaction. The imine having no substituent group on the nitrogen manufactured by means of the method of the present invention can synthesise diverse coupling products comprising amine compounds by means of reactions with diverse nucleophiles.

Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.

Abstract: In a method of forming a wiring structure, a carbon-containing layer may be formed on a substrate. A conductive layer may be formed on the carbon-containing layer, and the conductive layer may be formed to include a metal. The conductive layer and an upper portion of the carbon-containing layer may be etched to form a wiring and a carbon-containing layer pattern, respectively.

Abstract: A semiconductor device includes a semiconductor structure having a first wire extending in a first direction, an intermetallic insulating layer covering the semiconductor structure, a via structure penetrating the intermetallic insulating layer, and a second wire extending on the intermetallic insulating layer in a second direction at a predetermined angle with respect to the first direction, the second wire being connected to the first wire through the via structure and including first and second portions on each other, and a protruding portion protruding from at least one of the first and second portions, the protruding portion being at a boundary of the first and second portions.

Abstract: A vertical handover method in a heterogeneous overlay network communication system is provided. A vertical handover method for an overlay communication system including a plurality of base stations each serving at least one communication network technology to a mobile terminal includes determining whether a mobile terminal is located in a measurement region with reference to a vertical handover map in relation to a serving base station; detecting reachable base stations by activating all network interfaces when the mobile terminal locates in a measurement region; selecting one of the reachable base stations as a handover target base station; determining if the mobile terminal is located in a handover region with reference to the vertical handover map; and performing a handover if the mobile terminal is located in a handover region.

Abstract: An apparatus and method for the perforation of the skins or hulls of food pieces to more efficiently produce a dried, shelf-stable product. The apparatus contains two parallel and adjacent blade wheels positioned longitudinally within a frame in substantially the same horizontal plane at a distance from each other such that the blades' teeth contact product passing between the blade wheels and make perforations. Each blade wheel comprises a plurality of circular blades with a plurality of teeth around the circumference mounted on a rotatable shaft. In one aspect, a guard is provided for each blade wheel to ensure that no product remains on the blades after perforation. The shape, size and number of blades and the distance between the blade wheels may be modified with respect to the size and shape of the product and the strength of the product's skin or hull.

Abstract: An apparatus and method for transmitting a control signal using a symbol or bit pattern of an existing pilot channel, instead of using the time multiplexing method in the separate code channel or the existing physical channel, and reducing an error rate while a reception side detects the control signal are provided. For that purpose, a transmission side allocates transmission power corresponding to a pilot pattern determined according to the control information. A corresponding reception side detects control information based on a pilot pattern of pilot bits inserted in a dedicated physical channel (DPCH) and generates transmit power control (TPC) bits referring to a target reception power which is set based on the control information.

Abstract: An apparatus and method for transmitting a control signal using a symbol or bit pattern of an existing pilot channel, instead of using the time multiplexing method in the separate code channel or the existing physical channel, and reducing an error rate while a reception side detects the control signal are provided. For that purpose, a transmission side allocates transmission power corresponding to a pilot pattern determined according to the control information. A corresponding reception side detects control information based on a pilot pattern of pilot bits inserted in a dedicated physical channel (DPCH) and generates transmit power control (TPC) bits referring to a target reception power which is set based on the control information.