Patents by Inventor Jung-Hun Heo

Jung-Hun Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10484526
    Abstract: A method for providing contents corresponding to accessory devices and an electronic device thereof are disclosed. The electronic device includes a communication interface, at least one processor configured to be connected to the communication interface, and a memory connected to the at least one processor. The memory may store instructions that instruct the at least one processor to perform validity check on a first accessory device in response to detection of mounting of the first accessory device, determine a first content corresponding to the first accessory device, and provide a second content corresponding to a combination of the first accessory device and a second accessory device having an association relationship with the first accessory device, in response to detection of mounting of the second accessory device.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: November 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Wook Lee, Jung-Hun Kim, Seung Woo Park, Young Ho Rhee, Kihuk Lee, Cheolho Cheong, Chang-Ryong Heo, Hochul Hwang
  • Patent number: 10385303
    Abstract: The present invention relates to a method for selective cell attachment/detachment, cell patternization and cell harvesting by means of near infrared rays. More particularly, conducting polymers or metal oxides having exothermic characteristics upon irradiation of near infrared light is used as a cell culture scaffold, thus selectively attaching/detaching cells without an enzyme treatment. The scaffold has an effect of promoting proliferation or differentiation of stem cells, and therefore, can be used as a stem cell culture scaffold. The scaffold enables cell attachment/detachment without temporal or spatial restrictions, thus enabling cell patternization.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: August 20, 2019
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Eun Kyoung Kim, Hyun Ok Kim, Jung Mok You, Jeong Hun Kim, Tea Hoon Park, Byeong Gwan Kim, June Seok Heo, Han Soo Kim
  • Patent number: 10254813
    Abstract: Systems, apparatuses, and methods of power management for a system on a chip (SoC) are described. In one method, the operational states of the cores/processors of the SoC are monitored and, if a core/processor is in idle or standby mode, the rate of the clock signal driving a component, such as a memory interface, associated with the idle core/processor is reduced, thereby reducing power consumption.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: April 9, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hyo-Sang Jung, Sang-Wook Ju, Jung-Hun Heo
  • Patent number: 10075153
    Abstract: A low-power synchronizer circuit, a data processing circuit that incorporates the synchronizer circuit, and a synchronization method are provided. The synchronizer circuit includes a delay circuit for receiving and delaying an asynchronous input signal, a first flip-flop having an input terminal connected to an output terminal of the delay circuit, a clock terminal for receiving the asynchronous input signal, and a reset terminal for receiving the asynchronous input signal, a synchronizer connected to an output terminal of the first flip-flop, and a clock-gating circuit for receiving a clock signal and determining whether to supply the clock signal to the synchronizer in response to one of a first output value of the delay circuit and a second output value of the first flip-flop and a third output value of the synchronizer.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: September 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taek Kyun Shin, Jin Pyo Park, Soong Hyun Shin, Jung Hun Heo
  • Patent number: 9880608
    Abstract: An application processor includes a central processing unit (CPU), intellectual properties (IPs), a hardware power management unit (PMU) configured to determine whether the application processor is in system idle based on a first idle signal output from the CPU and output control signals as a result of the determination, and a clock signal supply control circuit configured to change an output signal supplied to the CPU and the IPs from clock signals to an oscillation clock signal, based on the control signals. The oscillation clock signal has a frequency lower than that of the clock signals.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Duk Kim, Gilles Dubost, Jinpyo Park, Seung Chull Suh, Jae Gon Lee, Sang Wook Ju, Jung Hun Heo
  • Patent number: 9870043
    Abstract: An integrated circuit, a method of controlling an operation timing of a memory device, an application processor, and a power manager are provided. The application processor includes: a power manager configured to determine a first operating power level, from among a plurality of operating power levels, to determine a first timing margin corresponding to the first operating power level, to generate a first gray code signal indicating the first timing margin, and to output the first gray code signal; and a first memory device configured to adjust an operation timing according to the first timing margin indicated by the first gray code signal, wherein the power manager is configured to provide the first operating power level to the first memory device.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: January 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Pil Lee, Su-Hyun Yun, Jae-Seung Choi, Jung-Hun Heo
  • Publication number: 20170265137
    Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.
    Type: Application
    Filed: December 27, 2016
    Publication date: September 14, 2017
    Inventors: TAEK KYUN SHIN, JUN HO SEO, JUNG HUN HEO
  • Publication number: 20170230038
    Abstract: A low-power synchronizer circuit, a data processing circuit that incorporates the synchronizer circuit, and a synchronization method are provided. The synchronizer circuit includes a delay circuit for receiving and delaying an asynchronous input signal, a first flip-flop having an input terminal connected to an output terminal of the delay circuit, a clock terminal for receiving the asynchronous input signal, and a reset terminal for receiving the asynchronous input signal, a synchronizer connected to an output terminal of the first flip-flop, and a clock-gating circuit for receiving a clock signal and determining whether to supply the clock signal to the synchronizer in response to one of a first output value of the delay circuit and a second output value of the first flip-flop and a third output value of the synchronizer.
    Type: Application
    Filed: December 27, 2016
    Publication date: August 10, 2017
    Inventors: TAEK KYUN SHIN, JIN PYO PARK, SOONG HYUN SHIN, JUNG HUN HEO
  • Patent number: 9489037
    Abstract: Provided is a power management device which includes a first regulator, a second regulator and a control register unit. The first regulator provides a first driving voltage to a first power domain of an application processor. The second regulator provides a second power domain of the application processor with a second driving voltage having a correlation with the first driving voltage. The control register unit controls, in response to a command from the application processor, a reference voltage generation circuit that provides a first reference voltage and a second reference voltage to the first regulator and the second regulator, respectively. The level of the first driving voltage is maintained in a first driving mode. The first driving voltage and the second driving voltage have a set voltage difference in a second driving mode.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: November 8, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hun Heo, Jong-Pil Lee
  • Publication number: 20160162001
    Abstract: Systems, apparatuses, and methods of power management for a system on a chip (SoC) are described. In one method, the operational states of the cores/processors of the SoC are monitored and, if a core/processor is in idle or standby mode, the rate of the clock signal driving a component, such as a memory interface, associated with the idle core/processor is reduced, thereby reducing power consumption.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 9, 2016
    Inventors: Hyo-Sang JUNG, Sang-Wook JU, Jung-Hun HEO
  • Patent number: 9298251
    Abstract: In a method of power control for a system-on-chip, output of at least one of a first wakeup request signal and a second wakeup request signal is controlled such that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval threshold. The first wakeup request signal and the second wakeup request signal are one of concurrent and consecutive wakeup request signals.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: March 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Gon Lee, Dong-Keun Kim, Si-Young Kim, Jung-Hun Heo
  • Publication number: 20160062437
    Abstract: An application processor includes a central processing unit (CPU), intellectual properties (IPs), a hardware power management unit (PMU) configured to determine whether the application processor is in system idle based on a first idle signal output from the CPU and output control signals as a result of the determination, and a clock signal supply control circuit configured to change an output signal supplied to the CPU and the IPs from clock signals to an oscillation clock signal, based on the control signals. The oscillation clock signal has a frequency lower than that of the clock signals.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 3, 2016
    Inventors: Young Duk KIM, Gilles DUBOST, Jinpyo PARK, Seung Chull SUH, Jae Gon LEE, Sang Wook JU, Jung Hun HEO
  • Publication number: 20150287444
    Abstract: An integrated circuit, a method of controlling an operation timing of a memory device, an application processor, and a power manager are provided. The application processor includes: a power manager configured to determine a first operating power level, from among a plurality of operating power levels, to determine a first timing margin corresponding to the first operating power level, to generate a first gray code signal indicating the first timing margin, and to output the first gray code signal; and a first memory device configured to adjust an operation timing according to the first timing margin indicated by the first gray code signal, wherein the power manager is configured to provide the first operating power level to the first memory device.
    Type: Application
    Filed: February 2, 2015
    Publication date: October 8, 2015
    Inventors: Jong-Pil LEE, Su-Hyun YUN, Jae-Seung CHOI, Jung-Hun HEO
  • Patent number: 9146880
    Abstract: An electronic system including a system-on-chip (SoC) providing access to a shared memory via a chip-to-chip link includes a memory device, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first central processing unit (CPU) and a memory access path configured to enable access to the memory device. The second semiconductor device is configured to access the memory device via the memory access path of the first semiconductor device. The second semiconductor device is permitted to access the memory device while the memory access path is active and the first CPU is inactive, and the memory access path is configured to become active without intervention of the first CPU.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: September 29, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-hun Heo, Jae-youl Kim, Jae-gon Lee, Nam-phil Jo
  • Publication number: 20150234452
    Abstract: Provided is a power management device which includes a first regulator, a second regulator and a control register unit. The first regulator provides a first driving voltage to a first power domain of an application processor. The second regulator provides a second power domain of the application processor with a second driving voltage having a correlation with the first driving voltage. The control register unit controls, in response to a command from the application processor, a reference voltage generation circuit that provides a first reference voltage and a second reference voltage to the first regulator and the second regulator, respectively. The level of the first driving voltage is maintained in a first driving mode. The first driving voltage and the second driving voltage have a set voltage difference in a second driving mode.
    Type: Application
    Filed: January 6, 2015
    Publication date: August 20, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hun HEO, Jong-Pil LEE
  • Patent number: 9054680
    Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: June 9, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Keun Kim, Sun Cheol Kwon, Si Young Kim, Jae Gon Lee, Jung Hun Heo
  • Publication number: 20150084675
    Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.
    Type: Application
    Filed: December 3, 2014
    Publication date: March 26, 2015
    Inventors: Dong Keun KIM, Sun Cheol KWON, Si Young KIM, Jae Gon LEE, Jung Hun HEO
  • Patent number: 8928385
    Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Keun Kim, Sun Cheol Kwon, Si Young Kim, Jae Gon Lee, Jung Hun Heo
  • Publication number: 20130318311
    Abstract: An electronic system including a system-on-chip (SoC) providing access to a shared memory via a chip-to-chip link includes a memory device, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first central processing unit (CPU) and a memory access path configured to enable access to the memory device. The second semiconductor device is configured to access the memory device via the memory access path of the first semiconductor device. The second semiconductor device is permitted to access the memory device while the memory access path is active and the first CPU is inactive, and the memory access path is configured to become active without intervention of the first CPU.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 28, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JUNG-HUN HEO, Jae-youl Kim, Jae-gon Lee, Nam-phil Jo
  • Publication number: 20130198545
    Abstract: In a method of power control for a system-on-chip, output of at least one of a first wakeup request signal and a second wakeup request signal is controlled such that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval threshold. The first wakeup request signal and the second wakeup request signal are one of concurrent and consecutive wakeup request signals.
    Type: Application
    Filed: November 15, 2012
    Publication date: August 1, 2013
    Inventors: Jae-Gon LEE, Dong-Keun KIM, Si-Young KIM, Jung-Hun HEO