Abstract: Provided is a power management device which includes a first regulator, a second regulator and a control register unit. The first regulator provides a first driving voltage to a first power domain of an application processor. The second regulator provides a second power domain of the application processor with a second driving voltage having a correlation with the first driving voltage. The control register unit controls, in response to a command from the application processor, a reference voltage generation circuit that provides a first reference voltage and a second reference voltage to the first regulator and the second regulator, respectively. The level of the first driving voltage is maintained in a first driving mode. The first driving voltage and the second driving voltage have a set voltage difference in a second driving mode.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: An electronic system including a system-on-chip (SoC) providing access to a shared memory via a chip-to-chip link includes a memory device, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first central processing unit (CPU) and a memory access path configured to enable access to the memory device. The second semiconductor device is configured to access the memory device via the memory access path of the first semiconductor device. The second semiconductor device is permitted to access the memory device while the memory access path is active and the first CPU is inactive, and the memory access path is configured to become active without intervention of the first CPU.

Abstract: In a method of power control for a system-on-chip, output of at least one of a first wakeup request signal and a second wakeup request signal is controlled such that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval threshold. The first wakeup request signal and the second wakeup request signal are one of concurrent and consecutive wakeup request signals.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: A mobile telecommunication device includes a digital baseband processing unit and an analog baseband processing circuit. The digital baseband processing unit is configured to extract a difference value of current ramping data of ramping data of ramping samples of a ramping profile from previous ramping data, the current ramping data and the previous ramping data having a first bit number, and to transmit the difference value to the analog baseband processing unit as sample difference ramping data having a second bit number which is smaller than a first bit number. The analog baseband processing unit configured to receive the sample difference ramping data, and to generate a ramping up/down signal of the first bit number based on the sample difference ramping data, wherein the ramping up/down signal controls an output power level of the mobile telecommunication device.

Abstract: A mobile telecommunication device includes a digital baseband processing unit and an analog baseband processing circuit. The digital baseband processing unit is configured to extract a difference value of current ramping data of ramping data of ramping samples of a ramping profile from previous ramping data, the current ramping data and the previous ramping data having a first bit number, and to transmit the difference value to the analog baseband processing unit as sample difference ramping data having a second bit number which is smaller than a first bit number. The analog baseband processing unit configured to receive the sample difference ramping data, and to generate a ramping up/down signal of the first bit number based on the sample difference ramping data, wherein the ramping up/down signal controls an output power level of the mobile telecommunication device.

Abstract: The n-to-m bit down-scaling correlates a plurality of n-bit correlation integral values into a plurality of m-bit data (n>m). The n-bit correlation integral values are obtained by correlating global positioning system (GPS) signals with a plurality of expected codes. Upper (n?m+1) bits are selected from the n-bit correlation integral values, and (n?m+1)-bit estimated absolute values are obtained. A significant bit of a maximum value of the upper (n?m+1) bits of the estimated absolute values is selected. A scale level is obtained based on the significant bit of the maximum value. The n-bit correlation integral values are down-scaled into the m-bit data based on the scale level. The amount of n-bit correlation integral values is reduced into m-bit correlation integral values by the down-scaling method, and thereby reducing a size of the memory for storing the correlation integral values.

Abstract: The n-to-m bit down-scaling correlates a plurality of n-bit correlation integral values into a plurality of m-bit data (n>m). The n-bit correlation integral values are obtained by correlating global positioning system (GPS) signals with a plurality of expected codes. Upper (n?m+1) bits are selected from the n-bit correlation integral values, and (n?m+1)-bit estimated absolute values are obtained. A significant bit of a maximum value of the upper (n?m+1) bits of the estimated absolute values is selected. A scale level is obtained based on the significant bit of the maximum value. The n-bit correlation integral values are down-scaled into the m-bit data based on the scale level. The amount of n-bit correlation integral values is reduced into m-bit correlation integral values by the down-scaling method, and thereby reducing a size of the memory for storing the correlation integral values.