Patents by Inventor Jung-hun Sung
Jung-hun Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154127Abstract: A positive electrode including a positive electrode active material layer disposed on at least one surface of a positive electrode current collector, the positive electrode active material layer including a lithium transition metal phosphate, a fluorine-based binder, and a conductive material. The lithium transition metal phosphate includes a carbon coating layer formed on a surface thereof, and a ratio (B/A) of a total weight (B) of the fluorine-based binder to a total weight (A) of carbon of the conductive material and the lithium transition metal phosphate in the positive electrode active material layer is 0.7 to 1.7.Type: ApplicationFiled: October 31, 2023Publication date: May 9, 2024Applicant: LG Energy Solution, Ltd.Inventors: Geum Jae Han, O Jong Kwon, Kwang Jin Kim, Ki Woong Kim, In Gu An, Jung Hun Choi, Da Young Lee, Jin Su Sung, Jeong Hwa Park
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Patent number: 10105943Abstract: Disclosed herein are a lamination apparatus which adheres substrates to a cover window having a curved surface and a lamination method using the same. The lamination apparatus includes a first jig on which a cover window is mounted, wherein a curved surface portion is formed in the cover window and a curvature center thereof is positioned behind the curved surface portion, a second jig on which a guide member is seated, wherein a substrate is mounted on the guide member and the guide member has a width greater than that of the substrate, and an interference member provided to interfere with both facing front surfaces of the guide member, wherein the interference member interferes with the guide member and the guide member is bent when the second jig approaches the first jig.Type: GrantFiled: April 27, 2016Date of Patent: October 23, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Do Hyung Kim, Dong-Hee Han, Do-Wan Kim, Byeong-Cheol Kim, Hak Rae Kim, Jung Hun Sung, Sung-Gwan Woo, Kyung Woon Jang, Chang Kyu Chung, Kyoung Hern Hong, Sung-Ju Hwang
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Publication number: 20170005063Abstract: A reflow apparatus include a carrier supporting a printed circuit board placed on a side thereof by using a vacuum pressure generated therein, and a processing chamber including a heating chamber and a cooling chamber, wherein the carrier includes at least one adsorption hole, formed in one side of the carrier, a vacuum space connected to the adsorption hole, and a vacuum control unit capable of maintaining or removing a vacuum pressure in the vacuum space by selective opening and closing a path connecting the vacuum space to the outside.Type: ApplicationFiled: March 24, 2016Publication date: January 5, 2017Inventors: Tae-gyu KANG, Kun-ho SONG, Jung-hun SUNG, Ju-young YU
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Publication number: 20160318293Abstract: Disclosed herein are a lamination apparatus which adheres substrates to a cover window having a curved surface and a lamination method using the same. The lamination apparatus includes a first jig on which a cover window is mounted, wherein a curved surface portion is formed in the cover window and a curvature center thereof is positioned behind the curved surface portion, a second jig on which a guide member is seated, wherein a substrate is mounted on the guide member and the guide member has a width greater than that of the substrate, and an interference member provided to interfere with both facing front surfaces of the guide member, wherein the interference member interferes with the guide member and the guide member is bent when the second jig approaches the first jig.Type: ApplicationFiled: April 27, 2016Publication date: November 3, 2016Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Do Hyung KIM, Dong-Hee HAN, Do-Wan KIM, Byeong-Cheol KIM, Hak Rae KIM, Jung Hun SUNG, Sung-Gwan WOO, Kyung Woon JANG, Chang Kyu CHUNG, Kyoung Hern HONG, Sung-Ju HWANG
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Patent number: 8823078Abstract: Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set.Type: GrantFiled: January 23, 2013Date of Patent: September 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-joo Kim, Yoon-dong Park, Jung-hun Sung, Yong-Koo Kyoung, Sang-moo Choi, Tae-hee Lee
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Patent number: 8674475Abstract: Provided are an antifuse and methods of operating and manufacturing the same. The antifuse may include first and second conductors separate from each other; a dielectric layer for an antifuse between the first and second conductors; and a diffusion layer between one of the first and second conductors and the dielectric layer.Type: GrantFiled: April 7, 2009Date of Patent: March 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Deok-kee Kim, Jung-hun Sung, Sang-moo Choi, Soo-jung Hwang
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Patent number: 8385122Abstract: Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set.Type: GrantFiled: January 14, 2010Date of Patent: February 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Won-joo Kim, Yoon-dong Park, Jung-hun Sung, Yong-koo Kyoung, Sang-moo Choi, Tae-hee Lee
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Patent number: 8062978Abstract: Crystalline aluminum oxide layers having increased energy band gap, charge trap memory devices including crystalline aluminum oxide layers and methods of manufacturing the same are provided. A method of forming an aluminum oxide layer having an increased energy band gap includes forming an amorphous aluminum oxide layer on a lower film, introducing hydrogen (H) or hydroxyl group (OH) into the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer including the H or OH.Type: GrantFiled: July 31, 2008Date of Patent: November 22, 2011Assignee: Samsung Electronics Co., Inc.Inventors: Sang-moo Choi, Jung-hun Sung, Kwang-soo Seol, Woong-chul Shin, Sang-jin Park
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Patent number: 8043952Abstract: Provided is a method of forming an aluminum oxide layer and a method of manufacturing a charge trap memory device using the same. The method of forming an aluminum oxide layer may include forming an amorphous aluminum oxide layer on an underlying layer, forming a crystalline auxiliary layer on the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer. Forming the crystalline auxiliary layer may include forming an amorphous auxiliary layer on the amorphous aluminum oxide layer; and crystallizing the amorphous auxiliary layer.Type: GrantFiled: May 22, 2008Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-moo Choi, Kwang-soo Seol, Woong-chul Shin, Sang-jin Park, Eun-ha Lee, Jung-hun Sung
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Patent number: 7929330Abstract: A memory device may include a cathode, an anode, a link connected to the anode, and a first connection element that connects the link to the cathode. The link and the anode may be located in a position lower than that of the cathode or the link and the anode may be located in a position higher than that of the cathode. Also, the cathode, the anode, the link, and the first connection element may be formed on the same plane.Type: GrantFiled: March 4, 2009Date of Patent: April 19, 2011Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry FoundationInventors: Deok-kee Kim, Ha-young You, Young-chang Joo, Jung-hun Sung, Soo-jung Hwang, Sung-yup Jung
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Patent number: 7782666Abstract: Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may include: a first control unit that allocates any one of 2N threshold voltage states to the N-bit data; a second control unit that spaces, by any one of a first interval and a second interval, adjacent threshold voltage states of the 2N threshold voltage states; and a programming unit that programs the N-bit data by generating, in each of the at least one multi-bit cell, a distribution state corresponding to the allocated threshold voltage state. The multi-bit programming apparatus can reduce an error rate when reading data.Type: GrantFiled: March 18, 2008Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung Lae Cho, Yoon Dong Park, Jun Jin Kong, Seung Hoon Lee, Jung Hun Sung, Sung-Jae Byun, Seung-Hwan Song, Donghun Yu, Sung Chung Park, Heeseok Eun
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Patent number: 7760551Abstract: A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell after the application of the supplementary pulse. A program state of the memory cell may be verified using a verification voltage after the application of the recovery voltage.Type: GrantFiled: September 10, 2008Date of Patent: July 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-jin Park, Kwang-soo Seol, Ki-hwan Choi, Jung-hun Sung, Sang-moo Choi
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Publication number: 20100177566Abstract: Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set.Type: ApplicationFiled: January 14, 2010Publication date: July 15, 2010Inventors: Won-joo Kim, Yoon-dong Park, Jung-hun Sung, Yong-koo Kyoung, Sang-moo Choi, Tae-hee Lee
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Patent number: 7751254Abstract: A method of programming a non-volatile memory device may include performing a first programming operation including applying a program voltage to a memory cell and verifying the memory cell using a first verification voltage. A perturbation pulse may be applied to the memory cell to facilitate thermalization of charges in the memory cell if the memory cell passes the verification using the first verification voltage. The memory cell may be verified using a second verification voltage greater than the first verification voltage after the perturbation pulse is applied.Type: GrantFiled: June 19, 2008Date of Patent: July 6, 2010Assignee: Samsung Electronic Co., Ltd.Inventors: Sang-jin Park, Kwang-soo Seol, Jung-hun Sung
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Patent number: 7675779Abstract: A non-volatile memory device includes memory transistors disposed on a semiconductor substrate in a NAND string. A string select transistor is disposed at a first end of the NAND string, and a ground select transistor is disposed at a second end of the NAN string. Bit lines are electrically connected to the semiconductor substrate outside of the string select transistor and a gate electrode of the ground select transistor.Type: GrantFiled: January 25, 2008Date of Patent: March 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Won-joo Kim, Yoon-dong Park, Seung-hoon Lee, Suk-pil Kim, Jae-woong Hyun, Jung-hun Sung, Tae-hee Lee
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Patent number: 7672167Abstract: A non-volatile memory device may include at least one string, at least one bit line corresponding to the at least one string, and/or a sensing transistor. The at least one string may include a plurality of memory cell transistors connected in series. The sensing transistor may include a gate configured to sense a voltage of the corresponding bit line. A threshold voltage of the sensing transistor may be higher than a voltage obtained by subtracting a given voltage from a voltage applied to read the corresponding bit line connected to a memory cell transistor to be read of the plurality of memory cell transistors.Type: GrantFiled: April 15, 2008Date of Patent: March 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-hun Sung, Ju-hee Park
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Patent number: 7668016Abstract: Non-volatile memory devices and methods of programming a non-volatile memory device in which electrons are moved between charge trap layers through a pad oxide layer are provided. The non-volatile memory devices include a charge trap layer on a semiconductor substrate and storing electrons, a pad oxide layer on the first charge trap layer, and a second trap layer on the pad oxide layer and storing electrons. In a programming mode in which data is written, the stored electrons are moved between a first position of the first charge trap layer and a first position of the second charge trap layer through the pad oxide layer or between a second position of the first charge trap layer and a second position of the second charge trap layer through the pad oxide layer.Type: GrantFiled: March 27, 2008Date of Patent: February 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-hun Sung, Kwang-soo Seol, Woong-chul Shin, Sang-jin Park, Sang-moo Choi
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Publication number: 20090256624Abstract: Provided are an antifuse and methods of operating and manufacturing the same. The antifuse may include first and second conductors separate from each other; a dielectric layer for an antifuse between the first and second conductors; and a diffusion layer between one of the first and second conductors and the dielectric layer.Type: ApplicationFiled: April 7, 2009Publication date: October 15, 2009Inventors: Deok-kee Kim, Jung-Hun Sung, Sang-moo Choi, Soo-Jung Hwang
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Publication number: 20090243787Abstract: Provided are an electrical fuse device and a method of operating the same. The electrical fuse device may include a fuse link having a multi layer structure with at least two metal layers. The number of metal layers that are blown, from among the at least two metal layers, may vary according to either the duration of application of voltage or the strength of voltage applied.Type: ApplicationFiled: March 26, 2009Publication date: October 1, 2009Inventors: Soo-Jung Hwang, Ha-young You, Deok-kee Kim, Jung-hun Sung, Young-chang Joo, Sung-yup Jung
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Publication number: 20090225581Abstract: A memory device may include a cathode, an anode, a link connected to the anode, and a first connection element that connects the link to the cathode. The link and the anode may be located in a position lower than that of the cathode or the link and the anode may be located in a position higher than that of the cathode. Also, the cathode, the anode, the link, and the first connection element may be formed on the same plane.Type: ApplicationFiled: March 4, 2009Publication date: September 10, 2009Inventors: Deok-kee Kim, Ha-young You, Young-chang Joo, Jung-hun Sung, Soo-jung Hwang, Sung-yup Jung