Patents by Inventor Jung-Hung CHANG
Jung-Hung CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250043045Abstract: A method for preparing a long-chain branched polypropylene includes subjecting a T-reagent to a polymerization reaction with propylene in the presence of a catalyst composition. The catalyst composition includes an alkylaluminoxane and a metallocene-based catalyst. The metallocene-based catalyst contains a metal selected from the group consisting of titanium (Ti), zirconium (Zr), and hafnium (Hf). The T-reagent having an alkenyl silyl functional group is selected from the group consisting of 1,2-bis[dimethyl(vinyl)silyl]ethane, dimethyldivinylsilane, 7-octenyldimethyl(vinyl)silane, 7-octenyldimethyl(allyl)silane, 4-(but-3-enyl)phenyldimethyl(vinyl)silane, 4-(but-3-enyl)phenyldimethyl(allyl)silane, and combinations thereof.Type: ApplicationFiled: July 30, 2024Publication date: February 6, 2025Inventors: Jing-Cherng Tsai, Kwang-Ming Chen, Jung-Hung Kao, Kun-Pei Hsieh, Chao-Shun Chang, Hsing-Chun Chen, Chun-Wei Chiu, Cheng-Hung Chiang, Yu-Chuan Sung, Shang-Lin Tsai, Yu-Sheng Lin
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Publication number: 20240395859Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.Type: ApplicationFiled: July 30, 2024Publication date: November 28, 2024Inventors: Zhi-Chang LIN, Chien Ning YAO, Shih-Cheng CHEN, Jung-Hung CHANG, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20240387738Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
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Publication number: 20240379875Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a first fin structure and a second fin structure over a substrate. The method includes forming a dummy gate structure over the first fin structure and the second fin structure, and removing a portion of the first fin structure and the second fin structure to form a first source/drain (S/D) recess and a second S/D recess. The method includes forming a first bottom layer in the first S/D recess and a second bottom layer in the second S/D recess, and forming a first dielectric liner layer over the first bottom layer. The method includes forming a first top layer over the first dielectric liner layer, and forming a first S/D structure over the first top layer and a second S/D structure over the second bottom layer.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien-Ning YAO, Tsung-Han CHUANG, Kai-Lin CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20240379855Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20240363703Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures, a gate stack surrounding the nanostructures, a first source/drain feature and a second source/drain feature adjoining a first side and a second side of the plurality of nanostructures, respectively, a first contact plug under and electrically connected to the first source/drain feature, a second contact plug over and electrically connected to the second source/drain feature, and an insulating layer surrounding the second contact plug and covering a top surface of the first source/drain feature.Type: ApplicationFiled: July 12, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hung CHANG, Lo Heng CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien-Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20240355901Abstract: A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.Type: ApplicationFiled: April 18, 2023Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Chih-Hao WANG, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Zhi-Chang LIN, Chien-Ning YAO, Tsung-Han CHUANG
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Publication number: 20240355907Abstract: A device includes: a stack of semiconductor channels; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; a source/drain contact on the source/drain region; and a gate spacer between the source/drain contact and the gate structure. The gate spacer includes: a first spacer layer in contact with the gate structure; and a second spacer layer between the first spacer layer and the source/drain contact, the second spacer layer having a first portion on the stack and a second portion on the first portion, the second portion being thinner than the first portion.Type: ApplicationFiled: August 25, 2023Publication date: October 24, 2024Inventors: Shih-Cheng CHEN, Jung-Hung CHANG, Chien Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
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Publication number: 20240355908Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.Type: ApplicationFiled: June 28, 2024Publication date: October 24, 2024Inventors: Tsung-Han CHUANG, Zhi-Chang LIN, Shih-Cheng CHEN, Jung-Hung CHANG, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
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Patent number: 12107169Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.Type: GrantFiled: July 10, 2023Date of Patent: October 1, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20240313118Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.Type: ApplicationFiled: May 24, 2024Publication date: September 19, 2024Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
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Publication number: 20240304687Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a polysilicon structure on a substrate, depositing a first spacer layer on the polysilicon structure, depositing a second spacer layer on the first spacer layer, forming a S/D region on the substrate, removing the second spacer layer, depositing a third spacer layer on the first spacer layer and on the S/D region, depositing an ESL on the third spacer layer, depositing an ILD layer on the etch stop layer, and replacing the polysilicon structure with a gate structure surrounding the nanostructured layer.Type: ApplicationFiled: August 11, 2023Publication date: September 12, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien Ning Yao, Chia-Hao Chang, Shih-Cheng Chen, Chih-Hao Wang, Chia-Cheng Tsai, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Tsung-Han Chuang
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Patent number: 12074204Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a protection layer and alternating first and second semiconductor layers over the protection layer. The method also includes etching the fin structure to form a source/drain recess, forming a sacrificial contact in the source/drain recess, forming a source/drain feature over the sacrificial contact in the source/drain recess, removing the first semiconductor layers of the fin structure, thereby forming a plurality of nanostructures, forming a gate stack wrapping around the nanostructures, removing the substrate thereby exposing the protection layer and the sacrificial contact and replacing the sacrificial contact with a contact plug.Type: GrantFiled: July 23, 2021Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Hung Chang, Lo Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien-Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20240282838Abstract: A device includes: a stack of nanostructures; a gate structure that wraps around the nanostructures; an isolation region between the stack of nanostructures and another stack of nanostructures adjacent thereto along a first direction; a source/drain region that abuts at least one of the nanostructures; and a spacer layer that is on sidewalls of the gate structure and on sidewalls of the source/drain region, the spacer layer covering an area between the source/drain region and a neighboring source/drain region of another transistor along the first direction.Type: ApplicationFiled: June 28, 2023Publication date: August 22, 2024Inventors: Jung-Hung CHANG, Tsung-Han CHUANG, Fu-Cheng CHANG, Shih-Cheng CHEN, Chia-Cheng TSAI, Kuo-Cheng CHIANG
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Publication number: 20240274473Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, a plurality of semiconductor layers disposed parallelly to each other and in contact with the source/drain epitaxial feature, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a dielectric region in the substrate below the source/drain epitaxial feature. The dielectric region includes a first oxidation region having a first dopant, and a second oxidation region having a second dopant different than the first dopant.Type: ApplicationFiled: April 23, 2024Publication date: August 15, 2024Inventors: I-Ming CHANG, Jung-Hung CHANG, Yao-Sheng HUANG, Huang-Lin CHAO, Chung-Liang CHENG, Hsiang-Pi CHANG
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Patent number: 12051736Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.Type: GrantFiled: August 31, 2021Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20240234419Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.Type: ApplicationFiled: March 22, 2024Publication date: July 11, 2024Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Lo Heng CHANG, CHIH-HAO WANG, Chien Ning YAO, Kuo-Cheng CHIANG
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Publication number: 20240194758Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.Type: ApplicationFiled: February 22, 2024Publication date: June 13, 2024Inventors: Zhi-Chang LIN, Kuan-Ting PAN, Shih-Cheng CHEN, Jung-Hung CHANG, Lo-Heng CHANG, Chien-Ning YAO, Kuo-Cheng CHIANG
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Patent number: 12009215Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A void is between the silicide layer and the dielectric fin.Type: GrantFiled: April 21, 2023Date of Patent: June 11, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsiung Lin, Jung-Hung Chang, Shih-Cheng Chen, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 12009216Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.Type: GrantFiled: July 25, 2023Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Hsiung Lin, Shih-Cheng Chen, Chih-Hao Wang, Jung-Hung Chang, Jui-Chien Huang