Patents by Inventor Jung-Hung CHANG

Jung-Hung CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984361
    Abstract: A semiconductor device includes a substrate, a plurality of nanosheets, a plurality of source/drain (S/D) features, and a gate stack. The substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin. The plurality of nanosheets is disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of nanosheets. A bottom surface of the plurality of source/drain (S/D) features on the first fin is equal to or lower than a bottom surface of the plurality of source/drain (S/D) features on the second fin. The gate stack wraps each of the plurality of nanosheets.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lo-Heng Chang, Chih-Hao Wang, Kuo-Cheng Chiang, Jung-Hung Chang, Pei-Hsun Wang
  • Publication number: 20240153958
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Application
    Filed: January 7, 2024
    Publication date: May 9, 2024
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11978674
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Ming Chang, Jung-Hung Chang, Chung-Liang Cheng, Hsiang-Pi Chang, Yao-Sheng Huang, Huang-Lin Chao
  • Patent number: 11948798
    Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Chang, Jung-Hau Shiu, Jen Hung Wang, Tze-Liang Lee
  • Patent number: 11901364
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20240021481
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base. The semiconductor device structure includes a first multilayer stack over the base. The first multilayer stack includes a first channel layer and a second channel layer over and spaced apart from the first channel layer. The semiconductor device structure includes a gate stack over the substrate. The gate stack wraps around the first multilayer stack. The semiconductor device structure includes an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the base. The semiconductor device structure includes a bottom spacer over the base. The semiconductor device structure includes a first source/drain structure over the bottom spacer and connected to the second channel layer.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wei TSAI, Yu-Xuan HUANG, Kuan-Lun CHENG, Chih-Hao WANG, Min CAO, Jung-Hung CHANG, Lo-Heng CHANG, Pei-Hsun WANG, Kuo-Cheng CHIANG
  • Publication number: 20240006536
    Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 4, 2024
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20230420513
    Abstract: An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source/drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source/drain region from the semiconductor substrate.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20230420520
    Abstract: In an embodiment, a device includes: first nanostructures; a first undoped semiconductor layer contacting a first dummy region of the first nanostructures; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructures; and a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.
    Type: Application
    Filed: January 5, 2023
    Publication date: December 28, 2023
    Inventors: Tsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kai-Lin Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11855096
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Patent number: 11855216
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Zhi-Chang Lin, Shih-Cheng Chen, Chih-Hao Wang, Pei-Hsun Wang, Lo-Heng Chang, Jung-Hung Chang
  • Publication number: 20230411527
    Abstract: A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a sidewall spacer. The channel layer is over a substrate. The gate structure wraps around the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The sidewall spacer is on a sidewall of the first source/drain epitaxial structure and includes a first dielectric layer and a second dielectric layer over the first dielectric layer and in contact with first source/drain epitaxial structure. The first dielectric layer and the second dielectric layer include different materials.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien Ning YAO, Tsung-Han CHUANG, Kai-Lin CHUANG, Kuo-Cheng CHIANG
  • Publication number: 20230395655
    Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes at least two active strip regions, a hybrid fin structure, and a gate stack. The hybrid fin structure is disposed between the at least two active strip regions. The gate stack is across the at least two active strip regions and the hybrid fin structure. A portion of the hybrid fin structure exposed by the gate stack is free of a high dielectric constant material.
    Type: Application
    Filed: June 5, 2022
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Chien-Ning Yao, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20230369456
    Abstract: A semiconductor device with back-side contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a stack of nanostructured semiconductor layers disposed adjacent to the first S/D region, a gate structure surrounding each of the nanostructured semiconductor layers, a first pair of spacers disposed on opposite sidewalls of the first S/D region, a second pair of spacers disposed on opposite sidewalls of the second S/D region, a third pair of spacers disposed on opposite sidewalls of the gate structure, a first contact structure disposed on a first surface of the first S/D region, and a second contact structure disposed on a second surface of the first S/D region. The first and second surfaces are opposite to each other. The first pair of spacers are disposed on opposite sidewalls of the second contact structure.
    Type: Application
    Filed: March 10, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Jung-Hung Chang, Shih-Cheng Chen, Chih-Hao Wang, Chien Ning Yao, Tsung-Han Chuang, Kuo-Cheng Chiang
  • Publication number: 20230369054
    Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Chun-Hsiung Lin, Shih-Cheng Chen, Chih-Hao Wang, Jung-Hung Chang, Jui-Chien Huang
  • Publication number: 20230335607
    Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11764065
    Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Lin, Shih-Cheng Chen, Chih-Hao Wang, Jung-Hung Chang, Jui-Chien Huang
  • Publication number: 20230260793
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A void is between the silicide layer and the dielectric fin.
    Type: Application
    Filed: April 21, 2023
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiung LIN, Jung-Hung CHANG, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11710774
    Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11699760
    Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: July 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang