Abstract: In accordance with an aspect of the present disclosure, there is provided a method for identifying a type of a vocoder. The method comprises acquiring identification target bitstreams encoded with a voice signal, acquiring, for each of a plurality of vocoders, a probability that each of the plurality of vocoders is related to the identification target bitstreams from the identification target bitstreams, acquiring waveforms for each decoder of each of the plurality of vocoders by inputting the identification target bitstreams to the each decoder of each of the plurality of vocoders, acquiring intelligibility values for each of the waveforms obtained for the each decoder of each of the plurality of vocoders from the waveforms, and determining the type of the vocoder related to the voice signal from the probability and the intelligibility values for each waveform.

Abstract: A data generating apparatus for generating noise environment noisy data is disclosed. The data generating apparatus according to the present application comprises a signal conversion unit configured to convert each of a noisy signal obtained in real environment and an original sound signal for the noisy signal into a noisy signal spectrum and an original sound signal spectrum in a short-time frequency domain; and a noisy signal generation training unit configured to train deep neural network to output the noisy signal spectrum corresponding to each short-time using the original sound signal spectrum as an input.

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

Abstract: Disclosed is a memory device. The memory device includes a memory cell array that includes a target cell, a row decoder that drive a word line, and a write driver and sense amplifier that are configured to drive a bit line and a source line. The row decoder is configured to drive the word line in a first program operation and a second program operation. Between a start of the first program operation and an end of the second program operation, the write driver and sense amplifier are configured to continuously drive a bit line connected to the target cell with a second driving voltage or drive a source line connected to the target cell with a third driving voltage.

Abstract: Disclosed is a memory device. The memory device includes a memory cell array that includes a target cell, a row decoder that drive a word line, and a write driver and sense amplifier that are configured to drive a bit line and a source line. The row decoder is configured to drive the word line in a first program operation and a second program operation. Between a start of the first program operation and an end of the second program operation, the write driver and sense amplifier are configured to continuously drive a bit line connected to the target cell with a second driving voltage or drive a source line connected to the target cell with a third driving voltage.

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

Abstract: Variable resistance memory devices are provided. A variable resistance memory device includes a memory cell that includes a switching device and a resistance sensing element that is connected in series with the switching device. The variable resistance memory device includes a word line that extends in a first direction and that is connected to a gate of the switching device. Moreover, the variable resistance memory device includes a plurality of bit lines extending in a second direction. A first connection node of a first bit line among the plurality of bit lines is electrically connected to the resistance sensing element. A second connection node of a second bit line, among the plurality of bit lines, adjacent the first bit line is electrically connected to the switching device.

Abstract: Variable resistance memory devices are provided. A variable resistance memory device includes a memory cell that includes a switching device and a resistance sensing element that is connected in series with the switching device. The variable resistance memory device includes a word line that extends in a first direction and that is connected to a gate of the switching device. Moreover, the variable resistance memory device includes a plurality of bit lines extending in a second direction. A first connection node of a first bit line among the plurality of bit lines is electrically connected to the resistance sensing element. A second connection node of a second bit line, among the plurality of bit lines, adjacent the first bit line is electrically connected to the switching device.

Abstract: A memory device may include a selected bit line connected to a first node and configured to receive a first current, a selected memory cell connected to the selected bit line, a reference bit line connected to a second node and configured to receive a second current, a reference memory cell connected between the reference bit line and a reference source line, a sub bit line connected to the second node, a sub memory cell connected between the sub bit line and a sub source line, and a sense amplifier configured to sense a voltage difference between the first node and the second node to determine data read from a selected memory cell connected to the selected bit line. The sub memory cell may include a cell transistor. A gate electrode of the cell transistor may be connected to the sub source line.

Abstract: A method for manufacturing a semiconductor device includes forming a magnetic tunnel junction (MTJ) structure comprising a magnetic fixed layer, a non-magnetic barrier layer and a magnetic free layer, and forming a metal oxide cap layer on the MTJ structure, wherein forming the metal oxide cap layer comprises depositing a metal layer on the magnetic free layer, performing an oxidation of the deposited metal layer to form an oxidized metal layer, and depositing a metal oxide layer on the oxidized metal layer.

Abstract: A memory device may include a selected bit line connected to a first node and configured to receive a first current, a selected memory cell connected to the selected bit line, a reference bit line connected to a second node and configured to receive a second current, a reference memory cell connected between the reference bit line and a reference source line, a sub bit line connected to the second node, a sub memory cell connected between the sub bit line and a sub source line, and a sense amplifier configured to sense a voltage difference between the first node and the second node to determine data read from a selected memory cell connected to the selected bit line. The sub memory cell may include a cell transistor. A gate electrode of the cell transistor may be connected to the sub source line.

Abstract: A method for manufacturing a semiconductor device includes forming a magnetic tunnel junction (MTJ) structure comprising a magnetic fixed layer, a non-magnetic barrier layer and a magnetic free layer, and forming a metal oxide cap layer on the MTJ structure, wherein forming the metal oxide cap layer comprises depositing a metal layer on the magnetic free layer, performing an oxidation of the deposited metal layer to form an oxidized metal layer, and depositing a metal oxide layer on the oxidized metal layer.

Abstract: A method for manufacturing a semiconductor device includes forming a magnetic tunnel junction (MTJ) structure comprising a magnetic fixed layer, a non-magnetic barrier layer on the non-magnetic barrier layer and the magnetic free layer on the non-magnetic barrier layer, forming an oxide cap layer on the magnetic free layer, and forming a noble metal cap layer on the oxide cap layer.

Abstract: A drum washing machine and a control method thereof. The drum washing machine includes a cabinet, a tub including a first tub part and a second tub part, a drum, an inlet provided at one side of the second tub part and supplying condensed water, and at least one flow path provided on one surface from among the inner surfaces of the second tub part opposite the drum and guiding flow of the condensed water to increase a contact area between the condensed water supplied from the inlet and the second tub part. The drum washing machine improves the structure of the tub to effectively inject condensed water, and may thus increase condensing efficiency. Further, the drum washing machine improves the structures of the tub and the drying duct, and may thus prevent accumulation of lint and lowering of performance of the drum washing machine.

Abstract: A memory system, and an operation method of a nonvolatile memory, include programming memory cells using a normal program pulse, reading out a first set of data from the memory cells, detecting failed cells based on the first set of data, storing information about the failed cells in a buffer, and reprogramming the failed cells using a reinforced program pulse in an idle state based on the information stored in the buffer.

Abstract: A resistive memory device and a sensing margin trimming method are provided. The resistive memory device includes a memory cell array and a trimming circuit. The memory cell array has a plurality of resistive memory cells. The trimming circuit generates a trimming signal according to a characteristic distribution shift value of the resistive memory cells. With the inventive concept, although a characteristic distribution of memory cells is varied, an erroneous read operation is minimized or reduced by securing a sensing margin stably. Accordingly, a fabrication yield of the resistive memory device is bettered.

Abstract: A resistance change memory device includes an array of resistance change memory cells, and a writing circuit configured to reset a selected memory cell to a high resistance state by supplying a RESET current to the selected memory cell in the array of resistance change memory cells in a program operation mode, wherein a level of the RESET current depends on a distribution of initial RESET currents for the array of resistance change memory cells.

Abstract: A memory system, and an operation method of a nonvolatile memory, include programming memory cells using a normal program pulse, reading out a first set of data from the memory cells, detecting failed cells based on the first set of data, storing information about the failed cells in a buffer, and reprogramming the failed cells using a reinforced program pulse in an idle state based on the information stored in the buffer.

Abstract: A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material.

Abstract: A method of operating a resistive memory device, includes; performing a data retention time test on a resistive memory cell array of a memory chip, determining a number of bad memory blocks of the resistive memory cell array on the basis of the data retention time test, determining on the basis of the number of bad memory blocks whether the memory chip is a refresh memory chip or a good memory chip, and upon determining that the memory chip is a refresh memory chip, performing at least one refresh operation on at least one bad memory block of the refresh memory chip.