Abstract: A drum washing machine and a control method thereof. The drum washing machine includes a cabinet, a tub including a first tub part and a second tub part, a drum, an inlet provided at one side of the second tub part and supplying condensed water, and at least one flow path provided on one surface from among the inner surfaces of the second tub part opposite the drum and guiding flow of the condensed water to increase a contact area between the condensed water supplied from the inlet and the second tub part. The drum washing machine improves the structure of the tub to effectively inject condensed water, and may thus increase condensing efficiency. Further, the drum washing machine improves the structures of the tub and the drying duct, and may thus prevent accumulation of lint and lowering of performance of the drum washing machine.

Abstract: A resistance change memory device includes an array of resistance change memory cells, and a writing circuit configured to reset a selected memory cell to a high resistance state by supplying a RESET current to the selected memory cell in the array of resistance change memory cells in a program operation mode, wherein a level of the RESET current depends on a distribution of initial RESET currents for the array of resistance change memory cells.

Abstract: A resistive memory device and a sensing margin trimming method are provided. The resistive memory device includes a memory cell array and a trimming circuit. The memory cell array has a plurality of resistive memory cells. The trimming circuit generates a trimming signal according to a characteristic distribution shift value of the resistive memory cells. With the inventive concept, although a characteristic distribution of memory cells is varied, an erroneous read operation is minimized or reduced by securing a sensing margin stably. Accordingly, a fabrication yield of the resistive memory device is bettered.

Abstract: A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material.

Abstract: The present invention relates to forming the material represented by the following formula (1) into a layer having hexagonal crystalline structure, which is different from the orthorhombic crystalline structure of the material in bulk phase, so that the material can be used more effectively in various fields requiring multiferroic properties by obtaining multiferroic properties enhanced than the conventional multiferroic materials. RMnO3, (R=Lanthanide) . . .

Abstract: A variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines.

Abstract: A phase change memory device and a write method thereof allow writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and writing data as volatile or non-volatile by applying a write pulse corresponding to the write mode, wherein, when power is not supplied to the phase change memory device, the non-volatile data is retained and the volatile data is not retained.

Abstract: A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current.

Abstract: A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current

Abstract: A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current.

Abstract: A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location occurs based on the monitored number of read cycles. Selectively pre-write verifying and writing of the received write data may include, for example, writing received write data to the selected memory cell region without pre-write verification responsive to the monitored number of read cycles being greater than a predetermined number of read cycles.

Abstract: Provided is a variable resistance memory device. The variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines.

Abstract: A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current

Abstract: A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location occurs based on the monitored number of read cycles.

Abstract: The present invention relates to forming the material represented by the following formula (1) into a layer having hexagonal crystalline structure, which is different from the orthorhombic crystalline structure of the material in bulk phase, so that the material can be used more effectively in various fields requiring multiferroic properties by obtaining multiferroic properties enhanced than the conventional multiferroic materials. RMnO3, (R=Lanthanide) . . .