Abstract: There is provided an upper limb rehabilitation robot including: a base frame that has a side to which a connecting support is rotatably laterally connected; a connecting shaft unit that is rotatably disposed at a side of the connecting support; a link unit that has a side coupled to the connecting shaft unit and the other side with an upper limb connector mounted to enable a person who needs rehabilitation to connect an upper limb; an active actuator that rotates a connecting shaft unit; and a manual actuator that generates resistant torque against rotation to the connecting shaft unit.

Abstract: The present invention relates to an aliphatic-aromatic copolyester resin composition with excellent hydrolysis resistance, wherein an unsaturated compound or an anhydride thereof is introduced into a molecular structure, and specifically, the aliphatic-aromatic copolyester resin composition can be manufactured into all molded products by extrusion, injection and the like, by solving problems with respect to physical properties, processability, reaction rates and water solubility of conventional biological resins.

Abstract: The present invention relates to a polysilicon resistor, a reference voltage circuit including the same, and a method for manufacturing the polysilicon resistor. The polysilicon resistor according includes a first polysilicon resistor and at least one of second polusilicon resistors, coupled to the first polysilicon resistor in series. The first polysilicon resistor and the at least one of the second polysilicon resistors are P-type polysilicon, and a doping concentration of the first polysilicon resistor is different from a doping concentration of the at least one of the second polysilicon resistors. The polysilicon resistor formed by serially coupling the first polysilicon resistor and the at least one of the second polysilicon resistors is applied with a constant current such that a reference voltage or a constant voltage is generated.

Abstract: This disclosure is related to a resistive device including a silicide pattern. A resistive device can include a substrate, and a first resistive layer disposed above the substrate. The resistive device can include a second resistive layer disposed on the first resistive layer and has a resistance different from a resistance of the first resistive layer. The resistive device can include a third resistive layer disposed on a first portion of the first resistive layer such that a second portion of the first resistive layer is disposed between the third resistive layer and the second resistive layer. The resistive layer can also include a conductive plug electrically connected to the third resistive layer.

Abstract: The present invention relates to a polysilicon resistor, a reference voltage circuit including the same, and a method for manufacturing the polysilicon resistor. The polysilicon resistor according includes a first polysilicon resistor and at least one of second polysilicon resistors, coupled to the first polysilicon resistor in series. The first polysilicon resistor and the at least one of the second polysilicon resistors are P-type polysilicon, and a doping concentration of the first polysilicon resistor is different from a doping concentration of the at least one of the second polysilicon resistors. The polysilicon resistor formed by serially coupling the first polysilicon resistor and the at least one of the second polysilicon resistors is applied with a constant current such that a reference voltage or a constant voltage is generated.

Abstract: The present invention relates to a polysilicon resistor, a reference voltage circuit including the same, and a method for manufacturing the polysilicon resistor. The polysilicon resistor according includes a first polysilicon resistor and at least one of second polysilicon resistors, coupled to the first polysilicon resistor in series. The first polysilicon resistor and the at least one of the second polysilicon resistors are P-type polysilicon, and a doping concentration of the first polysilicon resistor is different from a doping concentration of the at least one of the second polysilicon resistors. The polysilicon resistor formed by serially coupling the first polysilicon resistor and the at least one of the second polysilicon resistors is applied with a constant current such that a reference voltage or a constant voltage is generated.

Abstract: This invention relates to a method and apparatus for deposition of a diffused thin film, useful in the fabrication of semiconductors and for the surface DC-Bias coating of various tools. In order to coat the surface of a treatment object, such as semiconductors, various molded products, or various tools, with a thin film, one or more process factors selected from among a bias voltage, a gas quantity, an arc power, and a sputtering power are continuously and variably adjusted, whereby the composition ratio of the thin film which is formed on the surface of the treatment object not through a chemical reaction but through a physical method is continuously varied, thus manufacturing a thin film having high hardness. The composition ratio of the thin film to be deposited is selected depending on the end use thereof, thereby depositing the thin film having superior wear resistance, impact resistance, and heat resistance.

Abstract: A low power servo-controlled single clock ramp generator (100) includes a fast switched comparator (102), charge pump (110) and voltage-to-current converter (120) connected to provide a feedback control mechanism under control of a pulse comparison clock signal (pulse_comp) and a reset pulse clock signal (rst_pulse) that are generated from a single input clock signal (clkin) so that there are well defined time intervals between pulses in the pulse comparison clock signal and the reset pulse clock signal, thereby providing a ramp signal (Vramp_out) having a stable, frequency-independent amplitude that is not limited by the reference voltage.

Abstract: A method of modeling mismatch of capacitors and devices thereof. Unlike methods of only performing a measurement of capacitor mismatch using a floating gate technique, a method of modeling mismatch may include constructing an analog circuit having capacitors including a different ratio and/or size, and/or measuring capacitor mismatch values. A method of modeling mismatch may include extracting modeling parameters by applying measured mismatch values to a mismatch model, and/or calculating actual capacitor mismatch values by applying extracted modeling parameters and/or a ratio and/or size of actual capacitors to be modeled to a mismatch model. It may be possible to detect characteristics of an analog circuit based on calculated and/or actual capacitor mismatch values.

Abstract: Disclosed is a method for detecting properties of a Metal Oxide Silicon (MOS) varactor, which includes: establishing a MOS varactor model equation in conjunction with an area of a gate; calculating values of the coefficients of the MOS varactor model equation through measurements for test materials; and extracting the properties of a capacitor of the MOS varactor using the calculated values of the coefficients. According to the method, the MOS varactor model equation can be expressed by Cgate=[Cigate×Area+Cpgate×Perimeter]×N, wherein, Cgate denotes gate capacitance for voltage applied to the gate, Cigate denotes intrinsic gate capacitance, Cpgate denotes perimeter gate capacitance, and N denotes the number of gate fingers. The MOS varactor model equation can be applicable to various sized capacitors, so that it is possible to estimate a gate capacitance for voltage applied to a gate, considering the differences due to the surface shapes of a device.

Abstract: A low power servo-controlled single clock ramp generator (100) includes a fast switched comparator (102), charge pump (110) and voltage-to-current converter (120) connected to provide a feedback control mechanism under control of a pulse comparison clock signal (pulse_comp) and a reset pulse clock signal (rst_pulse) that are generated from a single input clock signal (clkin) so that there are well defined time intervals between pulses in the pulse comparison clock signal and the reset pulse clock signal, thereby providing a ramp signal (Vramp_out) having a stable, frequency-independent amplitude that is not limited by the reference voltage.