Patents by Inventor Jung-Jui Li

Jung-Jui Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395689
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Application
    Filed: July 25, 2023
    Publication date: December 7, 2023
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 11764280
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20230119022
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 11532748
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20210013338
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20200343357
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Application
    Filed: July 8, 2020
    Publication date: October 29, 2020
    Inventors: Po-Chi Wu, Chia-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10790394
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10714587
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20190252539
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10312149
    Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET structure includes a substrate, and the substrate includes a first region and a second region. The FinFET structure includes a first plurality of fin structures formed on the first region and a second plurality of fin structures formed on the second region. A density of the first plurality of fin structures is greater than a density of the second plurality of fin structures. The FinFET structure also includes a plurality of protruding structures between two adjacent second plurality of fin structures in the second region and an isolation structure formed on the substrate. The isolation structure has a gap height between the first plurality of fin structures and the second plurality of fin structures.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yi-Cheng Chao, Chai-Wei Chang, Po-Chi Wu, Jung-Jui Li
  • Publication number: 20190148241
    Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET structure includes a substrate, and the substrate includes a first region and a second region. The FinFET structure includes a first plurality of fin structures formed on the first region and a second plurality of fin structures formed on the second region. A density of the first plurality of fin structures is greater than a density of the second plurality of fin structures. The FinFET structure also includes a plurality of protruding structures between two adjacent second plurality of fin structures in the second region and an isolation structure formed on the substrate. The isolation structure has a gap height between the first plurality of fin structures and the second plurality of fin structures.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yi-Cheng CHAO, Chai-Wei CHANG, Po-Chi WU, Jung-Jui LI
  • Patent number: 10269963
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20180337246
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10090396
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 9978652
    Abstract: A method includes forming trenches on a semiconductor substrate, thereby defining regions for forming semiconductor devices; extracting a profile of the regions; determining an etch recipe based on at least the profile of the regions; filling in the trenches with a dielectric material; and performing an etching process to the dielectric material using the etch recipe.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Cheng Chao, Che-Cheng Chang, Po-Chi Wu, Jung-Jui Li
  • Patent number: 9818648
    Abstract: Methods for forming the fin field effect transistor (FinFET) device structure are provided. The method includes forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively, and a number of the first fin structures is greater than a number of the second fin structures. The method also includes forming a sacrificial layer on the first fin structures and the second fin structures and performing an etching process to the sacrificial layer to form an isolation structure on the substrate.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Cheng Chao, Chai-Wei Chang, Po-Chi Wu, Jung-Jui Li
  • Publication number: 20170309526
    Abstract: A method includes forming trenches on a semiconductor substrate, thereby defining regions for forming semiconductor devices; extracting a profile of the regions; determining an etch recipe based on at least the profile of the regions; filling in the trenches with a dielectric material; and performing an etching process to the dielectric material using the etch recipe.
    Type: Application
    Filed: June 2, 2017
    Publication date: October 26, 2017
    Inventors: Yi-Cheng Chao, Che-Cheng Chang, Po-Chi Wu, Jung-Jui Li
  • Publication number: 20170256640
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 7, 2017
    Inventors: Po-Chi Wu, Chai-wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 9704719
    Abstract: A method of fabricating a semiconductor device is disclosed. A substrate having an oxide layer is provided. At least a portion of the oxide layer is removed and forms a nitride layer. The nitride layer is removed, leaving nitride precipitates. The nitride precipitates are removed using phosphoric acid.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jung-Jui Li
  • Patent number: 9673112
    Abstract: The present disclosure provides a method for fabricating an integrated circuit in accordance with some embodiments. The method includes forming a trench on a semiconductor substrate, thereby defining fin active regions; extracting a profile of the fin active regions; determining an etch dosage according to the profile of the fin active regions; filling in the trench with a dielectric material; and performing an etching process to the dielectric material using the etch dosage, thereby recessing the dielectric material and defining a fin height of the fin active regions.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chao, Che-Cheng Chang, Po-Chi Wu, Jung-Jui Li