Patents by Inventor Jung-June Park

Jung-June Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220200422
    Abstract: The present invention relates to a stator coil winding machine including: a stator transfer unit adapted to transfer a linear type stator having a plurality of stator cores in directions of X and Y axes; a winding guide unit adapted to guide the transferred stator to coil winding; a winding unit adapted to wind a coil on the stator; a tension adjusting unit adapted to adjust tension on the coil being wound on the stator; and a controller adapted to control operations of the stator transfer unit, the winding guide unit, and the winding unit to allow the coil to be wound on the stator by means of three-phase Y connection, based on a previously set winding sequence.
    Type: Application
    Filed: April 14, 2020
    Publication date: June 23, 2022
    Inventors: Jung Ho LEE, Jung Woo HEO, Jeong Soo LIM, Chan Ho PARK, Tae June KIM
  • Patent number: 11368075
    Abstract: Provided is a stator coil winding machine including: a stator transfer unit adapted to transfer a linear type stator having a plurality of stator cores in directions of X and Y axes; a winding guide unit adapted to guide the transferred stator to coil winding; a winding unit adapted to wind a coil on the stator; a tension adjusting unit adapted to adjust tension on the coil being wound on the stator; and a controller adapted to control operations of the stator transfer unit, the winding guide unit, and the winding unit to allow the coil to be wound on the stator by means of three-phase Y connection on the basis of a previously set winding sequence.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 21, 2022
    Assignee: RAINBOW ROBOTICS
    Inventors: Jung Ho Lee, Jung Woo Heo, Jeong Soo Lim, Chan Ho Park, Tae June Kim
  • Patent number: 11362391
    Abstract: Disclosed is a battery pack including a battery module having a plurality of battery cells, and a heat dissipation member provided in contact with a bus bar at a side surface of the battery module where electrode leads of the battery cells and the bus bar coupled to the electrode leads are disposed.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: June 14, 2022
    Inventors: Kyung-Mo Kim, Ho-June Chi, Jeong-O Mun, Jin-Yong Park, Jung-Hoon Lee
  • Patent number: 11362402
    Abstract: A battery module includes a battery cell stack having a plurality of stacked battery cells and a plurality of bus bars respectively disposed adjacent to electrode leads respectively provided at the plurality of battery cells. The electrode leads respectively provided at the plurality of battery cells are electrically connected to the plurality of bus bars, respectively.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 14, 2022
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Ho-June Chi, Jung-Hoon Lee, Jeong-O Mun, Jin-Yong Park
  • Patent number: 11342631
    Abstract: A battery module improves electric connection between an electrode lead of a secondary battery and a bus bar. In detail, the battery module includes a plurality of pouch-type secondary batteries; and a bus bar contacted to at least two of first electrode leads and second electrode leads of the secondary batteries, wherein the bus bar includes at least two metal plates contacted and connected to at least two of the first electrode leads and the second electrode leads of at least two secondary batteries; and a main frame coupled to the metal plates, wherein at least one of the metal plates has a different kind of metal material from a material of the main frame.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 24, 2022
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Jung-Hoon Lee, Dal-Mo Kang, Sang-Woo Ryu, Jeong-O Mun, Jin-Yong Park, Ho-June Chi
  • Patent number: 11342632
    Abstract: A battery module includes a plurality of pouch-type secondary batteries arranged to be stacked in at least one direction, each secondary battery having an electrode lead, and a bus bar made of an electrically conductive material and bonded to at least two electrode leads of corresponding secondary batteries to electrically connect the corresponding secondary batteries to each other. Each bonded electrode lead may be configured to protrude from the corresponding secondary battery in a front and rear direction, and at least one of left and right side surfaces of each bonded electrode lead may be bonded to the bus bar.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 24, 2022
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Jung-Hoon Lee, Dal-Mo Kang, Sang-Woo Ryu, Jeong-O Mun, Jin-Yong Park, Ho-June Chi
  • Patent number: 11342038
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 11342621
    Abstract: A battery pack includes a battery module having a plurality of battery cells; a lower plate on which the plurality of battery modules are placed; a support member coupled to the lower plate to support the battery module; and a mounting nut coupled to the lower plate and coupled to the support member so that the battery module is fastened by means of a bolt, wherein the battery module is in contact with the support member.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 24, 2022
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Jin-Yong Park, Sang-Woo Ryu, Jeong-O Mun, Jung-Hoon Lee, Ho-June Chi
  • Publication number: 20220122675
    Abstract: A storage system includes: a memory controller which provides a clock signal; a buffer which receives the clock signal and re-drives the clock signal, the buffer including a sampler which receives a data signal and a data strobe signal regarding the data signal, and which outputs a data stream; and a nonvolatile memory, including: a first duty cycle corrector, which receives the clock signal outputs a corrected clock signal by performing a first duty correction operation on the clock signal; and a data strobe signal generator, which generates the data strobe signal based on the corrected clock signal and provides the data strobe signal to the buffer. The buffer receives the data strobe signal output from the nonvolatile memory, senses a duty ratio of the data strobe signal input to the sampler, and performs a second duty correction operation on the duty ratio of the input data strobe signal.
    Type: Application
    Filed: July 19, 2021
    Publication date: April 21, 2022
    Inventors: TongSung KIM, Dae Hoon NA, Jung-June PARK, Dong Ho SHIN, Byung Hoon JEONG, Young Min JO
  • Patent number: 11257531
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Publication number: 20210391023
    Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Inventors: Ji-yeon SHIN, Jeong-don IHM, Byung-hoon JEONG, Jung-june PARK
  • Patent number: 11114171
    Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-yeon Shin, Jeong-don Ihm, Byung-hoon Jeong, Jung-june Park
  • Publication number: 20210201964
    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
    Type: Application
    Filed: February 23, 2021
    Publication date: July 1, 2021
    Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
  • Patent number: 11024400
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Publication number: 20210151117
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 20, 2021
    Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
  • Publication number: 20210151089
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Application
    Filed: January 27, 2021
    Publication date: May 20, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Patent number: 10964360
    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10937474
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Publication number: 20200402592
    Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Inventors: Ji-yeon SHIN, Jeong-don IHM, Byung-hoon JEONG, Jung-june PARK
  • Patent number: 10770149
    Abstract: A non-volatile memory device includes an output driver to output a data signal. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-yeon Shin, Jeong-don Ihm, Byung-hoon Jeong, Jung-june Park