Patents by Inventor Jung-June Park
Jung-June Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11024400Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: GrantFiled: April 30, 2020Date of Patent: June 1, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Publication number: 20210151089Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.Type: ApplicationFiled: January 27, 2021Publication date: May 20, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
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Publication number: 20210151117Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: ApplicationFiled: January 29, 2021Publication date: May 20, 2021Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Patent number: 10964360Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.Type: GrantFiled: May 15, 2020Date of Patent: March 30, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Patent number: 10937474Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.Type: GrantFiled: October 30, 2019Date of Patent: March 2, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
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Publication number: 20200402592Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.Type: ApplicationFiled: September 2, 2020Publication date: December 24, 2020Inventors: Ji-yeon SHIN, Jeong-don IHM, Byung-hoon JEONG, Jung-june PARK
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Patent number: 10770149Abstract: A non-volatile memory device includes an output driver to output a data signal. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.Type: GrantFiled: July 30, 2018Date of Patent: September 8, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-yeon Shin, Jeong-don Ihm, Byung-hoon Jeong, Jung-june Park
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Publication number: 20200279591Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.Type: ApplicationFiled: May 15, 2020Publication date: September 3, 2020Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Publication number: 20200258589Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: ApplicationFiled: April 30, 2020Publication date: August 13, 2020Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Patent number: 10679717Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: GrantFiled: May 30, 2019Date of Patent: June 9, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Patent number: 10672436Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.Type: GrantFiled: August 8, 2018Date of Patent: June 2, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Publication number: 20200066317Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.Type: ApplicationFiled: October 30, 2019Publication date: February 27, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
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Patent number: 10559373Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: GrantFiled: July 1, 2019Date of Patent: February 11, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Patent number: 10482935Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.Type: GrantFiled: May 17, 2018Date of Patent: November 19, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-june Park, Jeong-Don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
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Publication number: 20190325979Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Publication number: 20190279733Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: ApplicationFiled: May 30, 2019Publication date: September 12, 2019Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Patent number: 10340022Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: GrantFiled: May 11, 2018Date of Patent: July 2, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Publication number: 20190139585Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.Type: ApplicationFiled: August 8, 2018Publication date: May 9, 2019Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Publication number: 20190139613Abstract: A non-volatile memory device includes an output driver to output a data signal. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.Type: ApplicationFiled: July 30, 2018Publication date: May 9, 2019Inventors: Ji-yeon SHIN, Jeong-don IHM, Byung-hoon JEONG, Jung-june PARK
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Publication number: 20180350414Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.Type: ApplicationFiled: May 17, 2018Publication date: December 6, 2018Applicant: Samsung Electronics Co, LtdInventors: Jung-june PARK, Jeong-Don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi