Patents by Inventor Jung-Kyu HAN

Jung-Kyu HAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12354883
    Abstract: Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: July 8, 2025
    Assignee: Intel Corporation
    Inventors: Bohan Shan, Dingying Xu, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Jung Kyu Han, Xiaoying Guo, Jeremy D. Ecton, Santosh Tripathi, Bai Nie, Haobo Chen, Kyle Jordan Arrington, Yue Deng, Wei Wei
  • Publication number: 20250218906
    Abstract: Embodiments disclosed herein include apparatuses with assemblies comprising passive electrical devices that are embedded in a core of a package substrate. In an embodiment, such an apparatus may comprise a substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface coupling the first surface to the second surface. In an embodiment the substrate comprises a passive electrical device. In an embodiment, a pad is on the first surface of the substrate, and a layer contacts the substrate. In an embodiment, the layer directly contacts the first surface and the sidewall surface of the substrate.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Inventors: Zhixin XIE, Ziqing HAN, Srinivas Venkata Ramanuja PIETAMBARAM, Jung Kyu HAN, Gang DUAN, Yingying ZHANG, Minglu LIU, Manni MO, Kyle ARRINGTON, Clay ARRINGTON, Bohan SHAN, Ryan CARRAZZONE, Yiqun BAI, Ziyin LIN, Jose WAIMIN, Dingying David XU, Hongxia FENG, Yongki MIN, Brandon C. MARIN
  • Publication number: 20250218885
    Abstract: Embodiments disclosed herein include components that are embedded in the core of a package substrate. In an embodiment, such an apparatus comprises a substrate with a cavity through a thickness of the substrate. In an embodiment, a component is in the cavity, and a first layer is in the cavity. In an embodiment the first layer is a dielectric material. In an embodiment, a second layer is in the cavity, and the second layer is a dielectric material that is a different material than the second layer.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Hong Seung YEON, Zhixin XIE, Anup PANINDRE, Yosuke KANAOKA, Jung Kyu HAN, Gang DUAN, Srinivas Venkata Ramanuja PIETAMBARAM
  • Publication number: 20250219040
    Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Tolga ACIKALIN, Soham AGARWAL, Benjamin T. DUONG, Jeremy D. ECTON, Kari E. HERNANDEZ, Brandon Christian MARIN, Pratyush MISHRA, Pratyasha MOHAPATRA, Srinivas Venkata Ramanuja PIETAMBARAM, Marcel M. SAID, Suddhasattwa NAD, Gang DUAN, Zhixin XIE, Jung Kyu HAN, Mohamed R. SABER, Shuren QU, Naiya SOETAN-DODD, Teng SUN, Yuxin FANG
  • Patent number: 12334422
    Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes an array of bumps to electrically couple the die to the substrate. Each of the bumps have a corresponding base. Different ones of the bases have different widths that vary spatially across the array of bumps.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: June 17, 2025
    Assignee: Intel Corporation
    Inventors: Kyle McElhinny, Onur Ozkan, Ali Lehaf, Xiaoying Guo, Steve Cho, Leonel Arana, Jung Kyu Han, Srinivas Pietambaram, Sashi Kandanur, Alexander Aguinaga
  • Publication number: 20250144857
    Abstract: Various aspects may provide a molding system. The molding system may include a molding unit which includes a first mold panel and a second mold panel. The first mold panel and the second mold panel may include a mold cavity which surrounds a semiconductor workpiece along a side surface of the semiconductor workpiece, with the first mold panel and the second mold panel engaged with the semiconductor workpiece. Various aspects may also provide a molding method which utilize the molding system.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Inventors: Zhixin XIE, Yi LI, Jesse JONES, Gang DUAN, Andrew JIMENEZ, Jung Kyu HAN, Yekan WANG
  • Publication number: 20250112136
    Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
  • Patent number: 12237759
    Abstract: Disclosed are a high-efficiency integrated power circuit with a reduced number of semiconductor elements and a control method thereof. A high-efficiency integrated power circuit of an integrated converter includes an input port, which is a first port, to which power for driving the integrated converter is input, a non-isolated port, which is a second port, for outputting, to outside the high-efficiency integrated power circuit, an allowable amount of power generated when power input through the input port passes through an inductor, and an isolated port, which is a third port, for conducing remaining power excepting power output through the non-isolated port and for maintaining the conducted remaining power inside the high-efficiency integrated power circuit.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: February 25, 2025
    Assignee: Korea Aerospace Research Institute
    Inventors: Jeong Eon Park, Jung Kyu Han
  • Publication number: 20250006645
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (PID) or an organic non-photoimageable dielectric (non-PID); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Xiao Liu, Bohan Shan, Dingying Xu, Gang Duan, Haobo Chen, Hongxia Feng, Jung Kyu Han, Xiaoying Guo, Zhixin Xie, Xiyu Hu, Robert Alan May, Kristof Kuwawi Darmawikarta, Changhua Liu, Yosuke Kanaoka
  • Publication number: 20250006671
    Abstract: An intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. The intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. The intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Marcel Arlan Wall, Hamid Azimi, Rahul N. Manepalli, Srinivas Venkata Ramanuja Pietambaram, Darko Grujicic, Steve Cho, Thomas L. Sounart, Gang Duan, Jung Kyu Han, Suddhasattwa Nad, Benjamin Duong, Shayan Kaviani
  • Publication number: 20240387396
    Abstract: Surface finishes for contacts and fiducial marks on integrated circuit package substrates and associated methods are disclosed. An example integrated circuit (IC) package substrate includes a first solder resist layer; a second solder resist layer opposite the first solder resist layer; and a fiducial marker including tin in an opening in the first solder resist layer.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 21, 2024
    Inventors: Jung Kyu Han, Gang Duan, Srinivas Pietambaram
  • Publication number: 20240332134
    Abstract: Methods and apparatus to mitigate electromigration are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, a contact pad at least partially extending though or positioned on the dielectric substrate, the contact pad including copper, and a metal interconnect coupled to the contact pad, the interconnect including indium.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Inventors: Liang He, Jung Kyu Han, Gang Duan
  • Publication number: 20240312924
    Abstract: Microelectronic devices, systems, and techniques are disclosed having package substrate land side fiducial structures that are readily distinguishable from adjacent interconnect structures during registration of the land side of the package substrate. The fiducial structure includes a ring shape, a double ring shape, a donut shape, a triangular shape, an H-shape, or an I-shape in contrast to the circular, square, or rectangular shape of the adjacent interconnect structure. The fiducial structure shape may also have a different size relative to the interconnect structure shape.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Applicant: Intel Corporation
    Inventors: Shishir Deshpande, Jung Kyu Han, Gang Duan, Srinivas Pietambaram
  • Patent number: 12060485
    Abstract: The present invention relates to a non-coating thermoplastic resin composition, a method for manufacturing a molded article by using the same, and a molded article manufactured by the same. More specifically, the present invention is characterized by providing the thermoplastic resin composition which contains polycarbonate, polysiloxane-polycarbonate copolymer, polyester, master-batched carbon black, and additives in specific contents and the molded article, which has excellent chemical resistance, mechanical properties, light resistance, hydrolysis resistance, and low glossiness, manufactured by using the same.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: August 13, 2024
    Assignees: Hyundai Motor Company, Kia Motors Corporation, Samyang Corporation
    Inventors: Seul Yi, Boo Youn An, Dae Sik Kim, Kyeong Hoon Jang, Min Woo Kwon, In Soo Han, Jin Gi Ahn, Do Young Bae, Hyung Jin Roh, Tae Jin An, Jung Kyu Han, Chul Jin Jo, Si Uk Cheon, Suk Woo Kang
  • Publication number: 20240243088
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 18, 2024
    Inventors: Brandon C. MARIN, Jung Kyu HAN, Thomas HEATON, Ali LEHAF, Rahul MANEPALLI, Srinivas PIETAMBARAM, Jacob VEHONSKY
  • Publication number: 20240222216
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate with a die coupled to the package substrate by a plurality of interconnects. In an embodiment, a first layer is on the package substrate surrounding the die, and a second layer is over and around the die. In an embodiment, the second layer underfills the plurality of interconnects, and the second layer has a different material composition than the first layer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Zhixin XIE, Jung Kyu HAN, Gang DUAN
  • Publication number: 20240213198
    Abstract: An electronic package comprises a first die having at least one first interconnect with solder over or under a first metal feature. A second die has at least one second interconnect to the first die, each second interconnect comprising a second metal feature comprising copper, solder over or under the second metal feature, and a layer between the solder and the second metal feature, wherein the layer comprises iron and has a different material than material of the first interconnect.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Applicant: Intel Corporation
    Inventors: Liang He, Yue Deng, Gang Duan, Jung Kyu Han, Ali Lehaf, Srinivas Pietambaram
  • Publication number: 20240210634
    Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a substrate and an optical fiber in the substrate. In an embodiment, a lens is optically coupled to the optical fiber. In an embodiment, the lens is a gradient index (GRIN) lens.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Inventors: Zhixin XIE, Jung Kyu HAN, Gang DUAN
  • Publication number: 20240213163
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes vertical connections with a layer including tin between the vertical connections and conductive traces. In selected examples, a layer including tin is used in conjunction with other interface layers. In selected examples, a layer including tin is used in all vertical connections.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Inventor: Jung Kyu Han
  • Publication number: 20240188223
    Abstract: There may be provided an apparatus. The apparatus may include a first dispensing unit and a second dispensing unit. The apparatus may further include a connection assembly coupled to the first dispensing unit and the second dispensing unit in a manner such that a position of the first dispensing unit or the second dispensing unit relative to the other of said first dispensing unit or second dispensing unit may be adjustable via the connection assembly.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 6, 2024
    Inventors: Zhixin XIE, Jung Kyu HAN, Gang DUAN