Abstract: Various aspects may provide a molding system. The molding system may include a molding unit which includes a first mold panel and a second mold panel. The first mold panel and the second mold panel may include a mold cavity which surrounds a semiconductor workpiece along a side surface of the semiconductor workpiece, with the first mold panel and the second mold panel engaged with the semiconductor workpiece. Various aspects may also provide a molding method which utilize the molding system.

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

Abstract: Disclosed are a high-efficiency integrated power circuit with a reduced number of semiconductor elements and a control method thereof. A high-efficiency integrated power circuit of an integrated converter includes an input port, which is a first port, to which power for driving the integrated converter is input, a non-isolated port, which is a second port, for outputting, to outside the high-efficiency integrated power circuit, an allowable amount of power generated when power input through the input port passes through an inductor, and an isolated port, which is a third port, for conducing remaining power excepting power output through the non-isolated port and for maintaining the conducted remaining power inside the high-efficiency integrated power circuit.

Abstract: An intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. The intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. The intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (PID) or an organic non-photoimageable dielectric (non-PID); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.

Abstract: Surface finishes for contacts and fiducial marks on integrated circuit package substrates and associated methods are disclosed. An example integrated circuit (IC) package substrate includes a first solder resist layer; a second solder resist layer opposite the first solder resist layer; and a fiducial marker including tin in an opening in the first solder resist layer.

Abstract: Methods and apparatus to mitigate electromigration are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, a contact pad at least partially extending though or positioned on the dielectric substrate, the contact pad including copper, and a metal interconnect coupled to the contact pad, the interconnect including indium.

Abstract: Microelectronic devices, systems, and techniques are disclosed having package substrate land side fiducial structures that are readily distinguishable from adjacent interconnect structures during registration of the land side of the package substrate. The fiducial structure includes a ring shape, a double ring shape, a donut shape, a triangular shape, an H-shape, or an I-shape in contrast to the circular, square, or rectangular shape of the adjacent interconnect structure. The fiducial structure shape may also have a different size relative to the interconnect structure shape.

Abstract: The present invention relates to a non-coating thermoplastic resin composition, a method for manufacturing a molded article by using the same, and a molded article manufactured by the same. More specifically, the present invention is characterized by providing the thermoplastic resin composition which contains polycarbonate, polysiloxane-polycarbonate copolymer, polyester, master-batched carbon black, and additives in specific contents and the molded article, which has excellent chemical resistance, mechanical properties, light resistance, hydrolysis resistance, and low glossiness, manufactured by using the same.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate with a die coupled to the package substrate by a plurality of interconnects. In an embodiment, a first layer is on the package substrate surrounding the die, and a second layer is over and around the die. In an embodiment, the second layer underfills the plurality of interconnects, and the second layer has a different material composition than the first layer.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes vertical connections with a layer including tin between the vertical connections and conductive traces. In selected examples, a layer including tin is used in conjunction with other interface layers. In selected examples, a layer including tin is used in all vertical connections.

Abstract: An electronic package comprises a first die having at least one first interconnect with solder over or under a first metal feature. A second die has at least one second interconnect to the first die, each second interconnect comprising a second metal feature comprising copper, solder over or under the second metal feature, and a layer between the solder and the second metal feature, wherein the layer comprises iron and has a different material than material of the first interconnect.

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a substrate and an optical fiber in the substrate. In an embodiment, a lens is optically coupled to the optical fiber. In an embodiment, the lens is a gradient index (GRIN) lens.

Abstract: The present disclosure relates to a system. The system may include a stage configured to support a substrate. The system may also include a bondhead configured to press a device against the substrate. The system may further include a light source configured to emit UV light towards the stage.

Abstract: The present disclosure is directed to a semiconductor carrier platform having a support panel with a top surface and a bottom surface, with the top surface providing a working surface for assembling IC packages using panel-level packaging technology. In an aspect, a backside molding layer may be positioned on the bottom surface of the support panel to prevent or correct any panel warpage. In another aspect, a removable film may be positioned between the bottom surface of the support panel and the backside molding layer to allow the support panel to be readily cleaned and reused.

Abstract: There may be provided an apparatus. The apparatus may include a first dispensing unit and a second dispensing unit. The apparatus may further include a connection assembly coupled to the first dispensing unit and the second dispensing unit in a manner such that a position of the first dispensing unit or the second dispensing unit relative to the other of said first dispensing unit or second dispensing unit may be adjustable via the connection assembly.

Abstract: Embodiments disclosed herein include a package architecture. In an embodiment, the package architecture comprises a first substrate with a first fiducial mark on a surface of the first substrate. In an embodiment, the package architecture further comprises a second substrate over the first substrate, where the second substrate comprises glass and a second fiducial mark on the second substrate, and where a footprint of the second fiducial mark at least partially overlaps a footprint of the first fiducial mark.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.

Abstract: An electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.