Patents by Inventor Jung Liao
Jung Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250136661Abstract: The present disclosure provides a pharmaceutical composition including an adipose tissue-derived extracellular vesicle and a biologic, and a use of the pharmaceutical composition for treating arthritis. The pharmaceutical composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.Type: ApplicationFiled: December 1, 2023Publication date: May 1, 2025Inventors: Hsiu-Jung Liao, Ssu-Jung Lu, Yu-Chen Tsai, Po-Cheng Lin, Ming-Hsi Chuang
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Patent number: 12289914Abstract: Provided are a nitride semiconductor device and a manufacturing method thereof. The nitride semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first metal layer, a second metal layer and a dielectric layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first metal layer is disposed in the second nitride semiconductor layer. The second metal layer is disposed on the second nitride semiconductor layer. The dielectric layer is disposed between the first metal layer and the second nitride semiconductor layer and/or between the second metal layer and the second nitride semiconductor layer.Type: GrantFiled: July 21, 2021Date of Patent: April 29, 2025Assignee: United Microelectronics Corp.Inventors: Chih Tung Yeh, Wen-Jung Liao
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Patent number: 12266696Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the I-V compound barrier layer are substantially coplanar.Type: GrantFiled: March 18, 2024Date of Patent: April 1, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Tung Yeh, Wen-Jung Liao
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Patent number: 12266701Abstract: A high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation layer and the mesa structure. The mesa structure includes a channel layer, a barrier layer on the channel layer, two opposite first edges extending along a first direction, and two opposite second edges extending along a second direction. The contact structure includes a body portion and a plurality of protruding portions. The body portion penetrates through the passivation layer. The protruding portions penetrate through the barrier layer and a portion of the channel layer. In a top view, the body portion overlaps the two opposite first edges of the mesa structure without overlapping the two opposite second edges of the mesa structure.Type: GrantFiled: May 18, 2023Date of Patent: April 1, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Tung Yeh, Chun-Liang Hou, Wen-Jung Liao, Chun-Ming Chang, Yi-Shan Hsu, Ruey-Chyr Lee
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Publication number: 20250082727Abstract: The present invention provides a method and a pharmaceutical composition for cartilage regeneration or treatment of a cartilage defect disease, e.g., degenerative osteoarthritis, which comprises CXCL14 protein, or the peptide fragment thereof. The method and pharmaceutical composition could further comprise stem cell-derived extracellular vesicles.Type: ApplicationFiled: September 6, 2024Publication date: March 13, 2025Applicant: FAR EASTERN MEMORIAL HOSPITALInventors: Hsiu-Jung LIAO, Chih-Hung CHANG, Yi-Shan SHEN, Chi-Ying HUANG
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Publication number: 20250060111Abstract: A relay fan capable of cooling a circuit board includes an air extraction motor, a heat dissipation base, and the circuit board. The air extraction motor includes an outer housing and a motor body. The outer housing has a first opening and a second opening opposite to each other, and the motor body is disposed in the outer housing. One end of the motor body has an exhaust outlet corresponding to the second opening. The heat dissipation base is disposed on the outer housing of the air extraction motor. The circuit board is electrically connected to the motor body of the air extraction motor and disposed on the heat dissipation base, and an airflow of the air extraction motor that is in an operation cools the heat dissipation base to further cool the circuit board.Type: ApplicationFiled: August 15, 2024Publication date: February 20, 2025Inventor: CHIN-JUNG LIAO
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Publication number: 20250060110Abstract: A split-type range hood includes a range hood body, an air duct, and a relay fan. The range hood body includes a chassis and a smoke collecting box that has an exhaust opening. The relay fan is disposed outside of the range hood body, and includes a suction motor, a heat-dissipation base, and a circuit board. The suction motor includes a motor body and an outer housing having first and second openings that are opposite to each other. Two ends of the air duct are in air communication with the exhaust opening and the first opening, respectively. The heat-dissipation base is disposed on the outer housing. The circuit board is electrically connected to the suction motor, and is disposed on the heat-dissipation base, so that the circuit board is cooled by cooling the heat-dissipation base with a suction airflow of the suction motor during operation.Type: ApplicationFiled: July 23, 2024Publication date: February 20, 2025Inventor: CHIN-JUNG LIAO
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Patent number: 12206000Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.Type: GrantFiled: January 18, 2024Date of Patent: January 21, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Tung Yeh, Chun-Liang Hou, Wen-Jung Liao, Chun-Ming Chang, Yi-Shan Hsu, Ruey-Chyr Lee
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Patent number: 12199176Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer and a recess. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recess is disposed in the group III-V barrier layer without penetrating the group III-V barrier layer in the active region.Type: GrantFiled: September 26, 2023Date of Patent: January 14, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ming Chang, Wen-Jung Liao
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Patent number: 12199175Abstract: The present invention provides a method of forming an insulating structure of a high electron mobility transistor (HEMT), firstly, a gallium nitride layer is formed, next, an aluminum gallium nitride layer is formed on the gallium nitride layer, then, a first patterned photoresist layer is formed on the aluminum gallium nitride layer, and a groove is formed in the gallium nitride layer and the aluminum gallium nitride layer, next, an insulating layer is formed and filling up the groove. Afterwards, a second patterned photoresist layer is formed on the insulating layer, wherein the pattern of the first patterned photoresist layer is complementary to the pattern of the second patterned photoresist layer, and part of the insulating layer is removed, then, the second patterned photoresist layer is removed, and an etching step is performed on the remaining insulating layer to remove part of the insulating layer again.Type: GrantFiled: May 29, 2022Date of Patent: January 14, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ming Chang, Wen-Jung Liao
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Publication number: 20250015173Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.Type: ApplicationFiled: September 17, 2024Publication date: January 9, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
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Publication number: 20250015142Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, a p-type doped III-V compound layer, an insulation layer, and a gate electrode. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar. The insulation layer is disposed on the III-V compound barrier layer. The insulation layer includes an opening located corresponding to the gate trench in a vertical direction. A part of the p-type doped III-V compound layer is disposed on the insulation layer in the vertical direction. The gate electrode is disposed on the p-type doped III-V compound layer.Type: ApplicationFiled: September 22, 2024Publication date: January 9, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Tung Yeh, Wen-Jung Liao
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Publication number: 20240408237Abstract: The present invention is related to a method and pharmaceutical composition for treating a cartilage damage in a subject (including a human or an animal), particularly osteoarthritis (OA), using extracellular vesicles (EVs) with SOX9 gene, called as “EV-SOX9”. The EV-SOX9 is obtained by encapsulating the SOX9 mRNA or the mRNA of its upstream and downstream gene in EVs, naïve EVs with high expression level of SOX9 mRNA or its upstream and downstream gene from different cell sources, or MSC-derived EV-SOX9, which is obtained by transferring the SOX9 gene or its upstream and downstream gene into a multipotent cell and collecting EVs.Type: ApplicationFiled: June 7, 2024Publication date: December 12, 2024Applicants: FAR EASTERN MEMORIAL HOSPITAL, NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Hsiu-Jung LIAO, Chih-Hung Chang, Chi-Ying Huang, Ly James Lee, Tai-Shan Cheng, Sin-Yu Chen
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Patent number: 12125903Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.Type: GrantFiled: September 21, 2023Date of Patent: October 22, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
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Patent number: 12125885Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar.Type: GrantFiled: August 12, 2021Date of Patent: October 22, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Tung Yeh, Wen-Jung Liao
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Publication number: 20240335034Abstract: A flip-down electronics cabinet includes a cabinet body, two first and two second sliding rails, a carrying tray, a door plate, and a circuit controlling device disposed in the cabinet body. The circuit controlling device includes a control interface, a controller, a master switch circuit, and a first and a second switch circuit. The control interface includes a master switch key, and a first and a second switch key. The controller enters an operation or a standby mode according to a received master switch signal. The master switch circuit is switched off when the controller enters the standby mode, and is switched on when the controller enters the operation mode. After entering the operation mode, the controller respectively controls the first switch circuit and the second switch circuit to be switched on or off according to a first switch signal and a second switch signal received thereby.Type: ApplicationFiled: April 2, 2024Publication date: October 10, 2024Inventor: CHIN-JUNG LIAO
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Patent number: 12113098Abstract: A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.Type: GrantFiled: March 20, 2023Date of Patent: October 8, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Tung Yeh, Kuang-Pi Lee, Wen-Jung Liao
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Publication number: 20240322008Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer, forming a second barrier layer on the first barrier layer, forming a first hard mask on the second barrier layer, removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.Type: ApplicationFiled: June 3, 2024Publication date: September 26, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou, Chih-Tung Yeh
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Patent number: 12048929Abstract: An array platform for three-dimensional cell culturing and drug testing and screening is disclosed. In the array platform, a hydrogel-cell mixture injection area is configured to inject a plurality of kinds of hydrogel-cell mixtures. Cell observation areas are connected to the hydrogel-cell mixture injection area. Electrodes are disposed under the cell observation areas and automatic cell quantification and three-dimensional cell co-arrangement of the plurality of kinds of hydrogel-cell mixtures in the cell observation areas through the electrodes to imitate a structure of body's tissues. A drug injection area is configured to inject a plurality of kinds of drugs. Drug combination generators respectively correspond to the cell observation areas and are connected to the drug injection area. Each drug combination generator has a microfluidic channel structure and configured to generate drug combinations according to the plurality of kinds of drugs.Type: GrantFiled: August 3, 2021Date of Patent: July 30, 2024Assignees: NATIONAL TSING HUA UNIVERSITY, TAIPEI MEDICAL UNIVERSITYInventors: Yu-Chen Chen, Han-Jung Liao, Kang-Yun Lee, Shu-Chuan Ho, Weilun Sun, Cheng-Hsien Liu
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Publication number: 20240234539Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.Type: ApplicationFiled: December 25, 2023Publication date: July 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou