Abstract: The present invention relates to an improved modified antibody, of which solubility is increased and which can be concentrated to have a high concentration and a method for manufacturing same, and to a modified antibody in which amino acids located in the framework region of the antibody are substituted, and a method for manufacturing same.

Abstract: Techniques are disclosed for generating a search index for a hierarchical data set so that a search query of the hierarchical data may return results without searching or analyzing the hierarchical data set itself. The techniques generate a flattened index that includes selected indexed attributes and additional attributes to be displayed with the indexed attributes. The techniques also generate a hierarchy representation of the hierarchical data. Using these generated data structures, query results may be returned without directly traversing the hierarchical data itself while also providing data and hierarchical context for the query results by overlaying the query results with nodes of the hierarchical representation or otherwise concurrently displaying the query results with nodes of the hierarchical representation.

Abstract: The present invention relates to an anti-VISTA antibody or an antigen binding fragment thereof, a nucleic acid coding for the same, a vector carrying the nucleic acid, a cell transformed with the vector, a method for preparing the antibody or an antigen binding fragment thereof, a composition for prevention or treatment of autoimmune disease, comprising the same antibody, and a composition for concurrent administration in combination with a PD-1 antibody or PD-L1 antibody.

Abstract: The present disclosure relates to an antibody to inhibit function of Angiopoietin-2 (Ang-2) by binding specifically to Ang-2, and directed to an anti-Ang2 antibody, a nucleic acid encoding the same, a vector comprising the nucleic acid, a cell transformed with the vector, a method of preparing the same, an angiogenesis inhibitor comprising the same, a composition for treating a disease related with Angiopoietin-2 activation and/or overproduction, a composition for diagnosing a disease related with Angiopoietin-2 activation and/or overproduction, a composition for treating eye disease or a composition for preventing or treating a cancer, and a composition for combining an antibody binding to Ang2 with a drug other than the antibody binding to Ang2.

Abstract: The present invention relates to an anti-VISTA antibody or an antigen binding fragment thereof, a nucleic acid coding for the same, a vector carrying the nucleic acid, a cell transformed with the vector, a method for preparing the antibody or an antigen binding fragment thereof, a composition for prevention or treatment of autoimmune disease, comprising the same antibody, and a composition for concurrent administration in combination with a PD-1 antibody or PD-L1 antibody.

Abstract: A chemical vapor deposition apparatus is disclosed, which is capable of improving the yield by an extension of a cleaning cycle, the chemical vapor deposition apparatus comprising a chamber with a substrate-supporting member for supporting a substrate; a chamber lid with plural first source supplying holes, the chamber lid installed over the chamber; plural source supplying pipes for supplying a process source to the plural first source supplying holes; a spraying-pipe supporting member with plural second source supplying holes corresponding to the plural first source supplying holes, the spraying-pipe supporting member detachably installed in the chamber lid; and plural source spraying pipes with plural third source supplying holes and plural source spraying holes, the plural source spraying pipes supported by the spraying-pipe supporting member, wherein the plural third source supplying holes are supplied with the process source through the plural second source supplying holes, and the plural source sprayin

Abstract: A chemical vapor deposition apparatus is disclosed, which is capable of improving the yield by an extension of a cleaning cycle, the chemical vapor deposition apparatus comprising a chamber with a substrate-supporting member for supporting a substrate; a chamber lid with plural first source supplying holes, the chamber lid installed over the chamber; plural source supplying pipes for supplying a process source to the plural first source supplying holes; a spraying-pipe supporting member with plural second source supplying holes corresponding to the plural first source supplying holes, the spraying-pipe supporting member detachably installed in the chamber lid; and plural source spraying pipes with plural third source supplying holes and plural source spraying holes, the plural source spraying pipes supported by the spraying-pipe supporting member, wherein the plural third source supplying holes are supplied with the process source through the plural second source supplying holes, and the plural source sprayin

Abstract: In a method of manufacturing an inspection apparatus for inspecting an electronic device, a sacrificial substrate is formed into a substrate pattern including a through-hole. A principal substrate including an internal wiring penetrating from a first surface to a second surface thereof is combined with the substrate pattern in such a configuration that the through-hole is positioned over the internal wiring, thereby forming a combined structure. A filling structure is formed in the through-hole of the substrate pattern, and the filling structure is electrically connected to the internal wiring of the principal substrate. The substrate pattern is removed from the combined structure, and thus the filling structure is formed into a probe structure on the principal substrate. The probe structure may be connected to the principal substrate without any adhesives such as a solder, to thereby prevent electrical resistance increase and excessive thermal stress.

Abstract: A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium crystalline layer or a dual layer in which a silicon-germanium crystalline layer covers a silicon crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode.

Abstract: A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium crystalline layer or a dual layer in which a silicon-germanium crystalline layer covers a silicon crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode.

Abstract: A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium single crystalline layer or a dual layer in which a silicon-germanium single crystalline layer covers a silicon single crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium single crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a single crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium single crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium single crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode.

Abstract: A method of forming polycrystalline silicon germanium gate electrode is disclosed. The method include the steps of forming gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma doping of germanium to the polycrystalline silicon layer. Generally, boron is doped to the polycrystalline silicon after the step of the plasma doping of germanium. The process of plasma doping of germanium comprises the step of forming germanium contained plasma and enhancing bias electric potential to substrate for the formulated germanium plasma to be accelerated and injected to the polycrystalline silicon layer revealed. If the present invention is applied to CMOS transistor device, doping mask for the germanium plasma doping can be used.

Abstract: A method of forming a semiconductor device using selective epitaxial growth (SEG) is provided. This method includes forming an insulating layer pattern having a window on a semiconductor substrate. The window exposes a predetermined region of the semiconductor substrate. The substrate having the window is cleaned, thereby removing any native oxide layer on the exposed substrate. The cleaned substrate is oxidized. Accordingly, a sacrificial oxide layer is formed thereon. The sacrificial oxide layer is removed. Thus, the exposed substrate has substantially no crystalline defects. A single crystalline semiconductor layer is then grown on the exposed substrate using SEG.

Abstract: A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium single crystalline layer or a dual layer in which a silicon-germanium single crystalline layer covers a silicon single crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium single crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a single crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium single crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium single crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode.

Abstract: A method of forming a semiconductor device using selective epitaxial growth (SEG) is provided. This method includes forming an insulating layer pattern having a window on a semiconductor substrate. The window exposes a predetermined region of the semiconductor substrate. The substrate having the window is cleaned, thereby removing any native oxide layer on the exposed substrate. The cleaned substrate is oxidized. Accordingly, a sacrificial oxide layer is formed thereon. The sacrificial oxide layer is removed. Thus, the exposed substrate has substantially no crystalline defects. A single crystalline semiconductor layer is then grown on the exposed substrate using SEG.

Abstract: A method of forming polycrystalline silicon germanium gate electrode is disclosed. The method include the steps of forming gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma doping of germanium to the polycrystalline silicon layer. Generally, boron is doped to the polycrystalline silicon after the step of the plasma doping of germanium. The process of plasma doping of germanium comprises the step of forming germanium contained plasma and enhancing bias electric potential to substrate for the formulated germanium plasma to be accelerated and injected to the polycrystalline silicon layer revealed. If the present invention is applied to CMOS transistor device, doping mask for the germanium plasma doping can be used.

Abstract: A method of selective epitaxial growth performed by sequentially and repeatedly introducing a source gas, an etching gas, and a reducing gas in the reaction chamber, wherein controlled epitaxial layer doping may be obtained by introducing a dopant source gas during introducing any one of the source gas, an etching gas, and a reducing gas, and thereby producing a smooth and uniform epitaxial layer on a predetermined region of a semiconductor substrate.

Abstract: A method of selective epitaxial growth performed by sequentially and repeatedly introducing a source gas, an etching gas, and a reducing gas in the reaction chamber, wherein controlled epitaxial layer doping may be obtained by introducing a dopant source gas during introducing any one of the source gas, an etching gas, and a reducing gas, and thereby producing a smooth and uniform epitaxial layer on a predetermined region of a semiconductor substrate.

Abstract: Methods for fabricating a tungsten nitride layer in a semiconductor substrate having an insulating layer formed thereon. The methods include forming a contact hole through the insulating layer. A tungsten nitride layer is then selectively deposited only in the contact hole by selectively reacting a nitrogen-containing gas with a tungsten source gas so as to prevent formation of tungsten nitride layer on the insulating layer outside the contact hole. Methods or fabricating metal wiring utilizing the methods of fabricating a tungsten nitride layer are also provided.

Abstract: A method of manufacturing a metal wiring layer in a semiconductor device, wherein an insulating layer is plasma treated before a tungsten nitride film is formed on the insulating layer. A metal, metal silicide or metal alloy thereafter being deposited over the tungsten nitride film.