Patents by Inventor Jung-Min Ha
Jung-Min Ha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12230749Abstract: A device for folding a pouch having first and second cup parts, first and second circumferential parts formed flat along circumferences thereof, respectively, includes: lower and upper nests on which the first and second cup parts are seated; first and second guides fixed to the lower and upper nests and having first and second protrusions protruding upwardly therefrom, the first and second protrusions in close contact with each other forming a support protrusion; and a pressing part allowing a connection part of the first and second circumferential parts to be in close contact with the support protrusion when the first and the second cup parts are seated on the lower and the upper nests, respectively, wherein when the pressing part causes the connection part and the support protrusion to be in contact, the upper nest rotates so that the second cup part is folded onto the first cup part.Type: GrantFiled: November 3, 2021Date of Patent: February 18, 2025Assignee: LG Energy Solution, Ltd.Inventors: Geun Hee Kim, Se Young Oh, Jung Su Oh, Jeong Min Ha
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Patent number: 12072878Abstract: Techniques are disclosed for generating a search index for a hierarchical data set so that a search query of the hierarchical data may return results without searching or analyzing the hierarchical data set itself. The techniques generate a flattened index that includes selected indexed attributes and additional attributes to be displayed with the indexed attributes. The techniques also generate a hierarchy representation of the hierarchical data. Using these generated data structures, query results may be returned without directly traversing the hierarchical data itself while also providing data and hierarchical context for the query results by overlaying the query results with nodes of the hierarchical representation or otherwise concurrently displaying the query results with nodes of the hierarchical representation.Type: GrantFiled: September 22, 2021Date of Patent: August 27, 2024Assignee: Oracle International CorporationInventors: George John Kellner, Jung Min Ha, Mark Pearson, Jingyi Han, Jennifer Darmour, Abhay Kumar, David Barry Groves, Hong Tuck Liew, Abburi Rahul Krishna Naga Karthik, Johnson Kunnel Joesph, Ann Deena Philip, Subramanya Sarma Kuchi Venkata Raghavendra, Jitin Sai Pichika, Srinivas Sureshkumar Guthivari
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Publication number: 20230303675Abstract: The present invention relates to an improved modified antibody, of which solubility is increased and which can be concentrated to have a high concentration and a method for manufacturing same, and to a modified antibody in which amino acids located in the framework region of the antibody are substituted, and a method for manufacturing same.Type: ApplicationFiled: August 19, 2021Publication date: September 28, 2023Inventors: Jongil KO, Jung Min HA, Joo Hyoung LEE, Ju Ryoung NAM, Weon Sup LEE
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Publication number: 20230090050Abstract: Techniques are disclosed for generating a search index for a hierarchical data set so that a search query of the hierarchical data may return results without searching or analyzing the hierarchical data set itself. The techniques generate a flattened index that includes selected indexed attributes and additional attributes to be displayed with the indexed attributes. The techniques also generate a hierarchy representation of the hierarchical data. Using these generated data structures, query results may be returned without directly traversing the hierarchical data itself while also providing data and hierarchical context for the query results by overlaying the query results with nodes of the hierarchical representation or otherwise concurrently displaying the query results with nodes of the hierarchical representation.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: Oracle International CorporationInventors: George John Kellner, Jung Min Ha, Mark Pearson, Jingyi Han, Jennifer Darmour, Abhay Kumar, David Barry Groves, Hong Tuck Liew, Abburi Rahul Krishna Naga Karthik, Johnson Kunnel Joesph, Ann Deena Philip, Subramanya Sarma Kuchi Venkata Raghavendra, Jitin Sai Pichika, Srinivas Sureshkumar Guthivari
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Patent number: 11407833Abstract: The present invention relates to an anti-VISTA antibody or an antigen binding fragment thereof, a nucleic acid coding for the same, a vector carrying the nucleic acid, a cell transformed with the vector, a method for preparing the antibody or an antigen binding fragment thereof, a composition for prevention or treatment of autoimmune disease, comprising the same antibody, and a composition for concurrent administration in combination with a PD-1 antibody or PD-L1 antibody.Type: GrantFiled: October 22, 2018Date of Patent: August 9, 2022Assignee: PHARMABCINE INC.Inventors: Youngae Lee, Sang Soon Byun, Jung Min Ha, Sungho Ahn, Keunhee Oh, Weon Sup Lee, MiJu Park, Eun Hee Lee, Do-yun Kim, Jin-San Yoo
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Publication number: 20220204603Abstract: The present disclosure relates to an antibody to inhibit function of Angiopoietin-2 (Ang-2) by binding specifically to Ang-2, and directed to an anti-Ang2 antibody, a nucleic acid encoding the same, a vector comprising the nucleic acid, a cell transformed with the vector, a method of preparing the same, an angiogenesis inhibitor comprising the same, a composition for treating a disease related with Angiopoietin-2 activation and/or overproduction, a composition for diagnosing a disease related with Angiopoietin-2 activation and/or overproduction, a composition for treating eye disease or a composition for preventing or treating a cancer, and a composition for combining an antibody binding to Ang2 with a drug other than the antibody binding to Ang2.Type: ApplicationFiled: February 25, 2020Publication date: June 30, 2022Inventors: Ju Ryoung NAM, Sang Soon BYUN, Jongil KO, Do-yun KIM, Joo Hyoung LEE, Jung Min HA, Cheonho PARK, Eun-Ah LEE, Weon Sup LEE, Jin-San YOO
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Publication number: 20200407449Abstract: The present invention relates to an anti-VISTA antibody or an antigen binding fragment thereof, a nucleic acid coding for the same, a vector carrying the nucleic acid, a cell transformed with the vector, a method for preparing the antibody or an antigen binding fragment thereof, a composition for prevention or treatment of autoimmune disease, comprising the same antibody, and a composition for concurrent administration in combination with a PD-1 antibody or PD-L1 antibody.Type: ApplicationFiled: October 22, 2018Publication date: December 31, 2020Inventors: Youngae Lee, Sang Soon Byun, Jung Min Ha, Sungho Ahn, Keunhee Oh, Weon Sup Lee, MiJu Park, Eun Hee Lee, Do-yun Kim, Jin-San Yoo
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Patent number: 8398769Abstract: A chemical vapor deposition apparatus is disclosed, which is capable of improving the yield by an extension of a cleaning cycle, the chemical vapor deposition apparatus comprising a chamber with a substrate-supporting member for supporting a substrate; a chamber lid with plural first source supplying holes, the chamber lid installed over the chamber; plural source supplying pipes for supplying a process source to the plural first source supplying holes; a spraying-pipe supporting member with plural second source supplying holes corresponding to the plural first source supplying holes, the spraying-pipe supporting member detachably installed in the chamber lid; and plural source spraying pipes with plural third source supplying holes and plural source spraying holes, the plural source spraying pipes supported by the spraying-pipe supporting member, wherein the plural third source supplying holes are supplied with the process source through the plural second source supplying holes, and the plural source sprayinType: GrantFiled: May 27, 2010Date of Patent: March 19, 2013Assignee: Jusung Engineering Co., Ltd.Inventors: Sang Ki Park, Jung Min Ha, Seong Ryong Hwang
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Publication number: 20100307416Abstract: A chemical vapor deposition apparatus is disclosed, which is capable of improving the yield by an extension of a cleaning cycle, the chemical vapor deposition apparatus comprising a chamber with a substrate-supporting member for supporting a substrate; a chamber lid with plural first source supplying holes, the chamber lid installed over the chamber; plural source supplying pipes for supplying a process source to the plural first source supplying holes; a spraying-pipe supporting member with plural second source supplying holes corresponding to the plural first source supplying holes, the spraying-pipe supporting member detachably installed in the chamber lid; and plural source spraying pipes with plural third source supplying holes and plural source spraying holes, the plural source spraying pipes supported by the spraying-pipe supporting member, wherein the plural third source supplying holes are supplied with the process source through the plural second source supplying holes, and the plural source sprayinType: ApplicationFiled: May 27, 2010Publication date: December 9, 2010Inventors: Sang Ki PARK, Jung Min Ha, Seong Ryong Hwang
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Publication number: 20100242275Abstract: In a method of manufacturing an inspection apparatus for inspecting an electronic device, a sacrificial substrate is formed into a substrate pattern including a through-hole. A principal substrate including an internal wiring penetrating from a first surface to a second surface thereof is combined with the substrate pattern in such a configuration that the through-hole is positioned over the internal wiring, thereby forming a combined structure. A filling structure is formed in the through-hole of the substrate pattern, and the filling structure is electrically connected to the internal wiring of the principal substrate. The substrate pattern is removed from the combined structure, and thus the filling structure is formed into a probe structure on the principal substrate. The probe structure may be connected to the principal substrate without any adhesives such as a solder, to thereby prevent electrical resistance increase and excessive thermal stress.Type: ApplicationFiled: October 22, 2008Publication date: September 30, 2010Inventors: Woo-Chang Choi, Jung-Min Ha, Yong-Ji Lee, Ji-Hee Hwang, Sung-Jae Oh
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Patent number: 7326587Abstract: A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium crystalline layer or a dual layer in which a silicon-germanium crystalline layer covers a silicon crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode.Type: GrantFiled: June 14, 2005Date of Patent: February 5, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Woo Park, Jung-Min Ha
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Publication number: 20050230732Abstract: A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium crystalline layer or a dual layer in which a silicon-germanium crystalline layer covers a silicon crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode.Type: ApplicationFiled: June 14, 2005Publication date: October 20, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-Woo Park, Jung-Min Ha
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Patent number: 6927444Abstract: A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium single crystalline layer or a dual layer in which a silicon-germanium single crystalline layer covers a silicon single crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium single crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a single crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium single crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium single crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode.Type: GrantFiled: May 30, 2002Date of Patent: August 9, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Woo Park, Jung-Min Ha
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Patent number: 6596605Abstract: A method of forming polycrystalline silicon germanium gate electrode is disclosed. The method include the steps of forming gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma doping of germanium to the polycrystalline silicon layer. Generally, boron is doped to the polycrystalline silicon after the step of the plasma doping of germanium. The process of plasma doping of germanium comprises the step of forming germanium contained plasma and enhancing bias electric potential to substrate for the formulated germanium plasma to be accelerated and injected to the polycrystalline silicon layer revealed. If the present invention is applied to CMOS transistor device, doping mask for the germanium plasma doping can be used.Type: GrantFiled: December 28, 2000Date of Patent: July 22, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Min Ha, Jung-Woo Park
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Patent number: 6562707Abstract: A method of forming a semiconductor device using selective epitaxial growth (SEG) is provided. This method includes forming an insulating layer pattern having a window on a semiconductor substrate. The window exposes a predetermined region of the semiconductor substrate. The substrate having the window is cleaned, thereby removing any native oxide layer on the exposed substrate. The cleaned substrate is oxidized. Accordingly, a sacrificial oxide layer is formed thereon. The sacrificial oxide layer is removed. Thus, the exposed substrate has substantially no crystalline defects. A single crystalline semiconductor layer is then grown on the exposed substrate using SEG.Type: GrantFiled: January 10, 2002Date of Patent: May 13, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Ryol Ryu, Jung-Woo Park, Jung-Min Ha, Si-Young Choi
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Publication number: 20030017667Abstract: A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium single crystalline layer or a dual layer in which a silicon-germanium single crystalline layer covers a silicon single crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium single crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a single crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium single crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium single crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode.Type: ApplicationFiled: May 30, 2002Publication date: January 23, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-Woo Park, Jung-Min Ha
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Publication number: 20020146888Abstract: A method of forming a semiconductor device using selective epitaxial growth (SEG) is provided. This method includes forming an insulating layer pattern having a window on a semiconductor substrate. The window exposes a predetermined region of the semiconductor substrate. The substrate having the window is cleaned, thereby removing any native oxide layer on the exposed substrate. The cleaned substrate is oxidized. Accordingly, a sacrificial oxide layer is formed thereon. The sacrificial oxide layer is removed. Thus, the exposed substrate has substantially no crystalline defects. A single crystalline semiconductor layer is then grown on the exposed substrate using SEG.Type: ApplicationFiled: January 10, 2002Publication date: October 10, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-Ryol Ryu, Jung-Woo Park, Jung-Min Ha, Si-Young Choi
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Publication number: 20020072182Abstract: A method of forming polycrystalline silicon germanium gate electrode is disclosed. The method include the steps of forming gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma doping of germanium to the polycrystalline silicon layer. Generally, boron is doped to the polycrystalline silicon after the step of the plasma doping of germanium. The process of plasma doping of germanium comprises the step of forming germanium contained plasma and enhancing bias electric potential to substrate for the formulated germanium plasma to be accelerated and injected to the polycrystalline silicon layer revealed. If the present invention is applied to CMOS transistor device, doping mask for the germanium plasma doping can be used.Type: ApplicationFiled: December 28, 2000Publication date: June 13, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-Min Ha, Jung-Woo Park
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Patent number: 6391749Abstract: A method of selective epitaxial growth performed by sequentially and repeatedly introducing a source gas, an etching gas, and a reducing gas in the reaction chamber, wherein controlled epitaxial layer doping may be obtained by introducing a dopant source gas during introducing any one of the source gas, an etching gas, and a reducing gas, and thereby producing a smooth and uniform epitaxial layer on a predetermined region of a semiconductor substrate.Type: GrantFiled: June 15, 2001Date of Patent: May 21, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Woo Park, Jong-Ryul Yoo, Jung-Min Ha, Si-Young Choi
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Publication number: 20020022347Abstract: A method of selective epitaxial growth performed by sequentially and repeatedly introducing a source gas, an etching gas, and a reducing gas in the reaction chamber, wherein controlled epitaxial layer doping may be obtained by introducing a dopant source gas during introducing any one of the source gas, an etching gas, and a reducing gas, and thereby producing a smooth and uniform epitaxial layer on a predetermined region of a semiconductor substrate.Type: ApplicationFiled: June 15, 2001Publication date: February 21, 2002Inventors: Jung-Woo Park, Jong-Ryul Yoo, Jung-Min Ha, Si-Young Choi