Patents by Inventor Jung Myoung SHIM

Jung Myoung SHIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935926
    Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: March 19, 2024
    Assignee: SK hynix Inc.
    Inventors: Hyeng-Woo Eom, Jung-Myoung Shim, Young-Ho Yang, Kwang-Wook Lee, Won-Joon Choi
  • Patent number: 11588026
    Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: February 21, 2023
    Assignee: SK hynix Inc.
    Inventors: Hyeng-Woo Eom, Jung-Myoung Shim, Young-Ho Yang, Kwang-Wook Lee, Won-Joon Choi
  • Publication number: 20200388686
    Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.
    Type: Application
    Filed: January 13, 2020
    Publication date: December 10, 2020
    Inventors: Hyeng-Woo EOM, Jung-Myoung SHIM, Young-Ho YANG, Kwang-Wook LEE, Won-Joon CHOI
  • Patent number: 10714499
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 14, 2020
    Assignee: SK hynix Inc.
    Inventors: Won Joon Choi, Min Sung Ko, Kyeong Bae Kim, Jong Gi Kim, Dong Sun Sheen, Jung Myoung Shim, Young Ho Yang, Hyeng Woo Eom, Kwang Wook Lee, Woo Jae Chung
  • Publication number: 20190319045
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 17, 2019
    Inventors: Won Joon CHOI, Min Sung KO, Kyeong Bae KIM, Jong Gi KIM, Dong Sun SHEEN, Jung Myoung SHIM, Young Ho YANG, Hyeng Woo EOM, Kwang Wook LEE, Woo Jae CHUNG
  • Patent number: 10373973
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventors: Won Joon Choi, Min Sung Ko, Kyeong Bae Kim, Jong Gi Kim, Dong Sun Sheen, Jung Myoung Shim, Young Ho Yang, Hyeng Woo Eom, Kwang Wook Lee, Woo Jae Chung
  • Publication number: 20190081066
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Application
    Filed: April 24, 2018
    Publication date: March 14, 2019
    Inventors: Won Joon CHOI, Min Sung KO, Kyeong Bae KIM, Jong Gi KIM, Dong Sun SHEEN, Jung Myoung SHIM, Young Ho YANG, Hyeng Woo EOM, Kwang Wook LEE, Woo Jae CHUNG
  • Patent number: 9947543
    Abstract: The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The method of manufacturing a semiconductor memory device, includes forming a tunnel insulation layer and a floating gate on a semiconductor substrate of an active region, forming a trench in the semiconductor substrate of an isolation region, forming, in the trench, a sacrificial layer having an upper surface positioned higher than a surface of the semiconductor substrate, forming a capping layer over the sacrificial layer, and forming an air gap by removing the sacrificial layer without removing the capping layer.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: April 17, 2018
    Assignee: SK Hynix Inc.
    Inventors: Tae Kyung Kim, Jung Myoung Shim, Myung Kyu Ahn, Sung Soon Kim, Woo Duck Jung
  • Publication number: 20160111291
    Abstract: The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The method of manufacturing a semiconductor memory device, includes forming a tunnel insulation layer and a floating gate on a semiconductor substrate of an active region, forming a trench in the semiconductor substrate of an isolation region, forming, in the trench, a sacrificial layer having an upper surface positioned higher than a surface of the semiconductor substrate, forming a capping layer over the sacrificial layer, and forming an air gap by removing the sacrificial layer without removing the capping layer.
    Type: Application
    Filed: November 23, 2015
    Publication date: April 21, 2016
    Inventors: Tae Kyung KIM, Jung Myoung SHIM, Myung Kyu AHN, Sung Soon KIM, Woo Duck JUNG
  • Publication number: 20140042518
    Abstract: A semiconductor device includes isolation layers formed in isolation regions defined between active regions of a semiconductor substrate, wherein each of the isolation layers includes a first air gap, word lines formed over the semiconductor substrate in a direction crossing the isolation layers, wherein each of the word lines includes a stacked structure of a tunnel insulating layer, a floating gate, a dielectric layer and a control gate, and including insulating layers between the word lines, wherein a width of the floating gate is greater than a width of each active region.
    Type: Application
    Filed: December 14, 2012
    Publication date: February 13, 2014
    Applicant: SK HYNIX INC.
    Inventor: Jung Myoung SHIM
  • Publication number: 20140042516
    Abstract: The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The semiconductor memory device includes a semiconductor substrate in which isolation regions and active regions are defined, gate lines formed on the semiconductor substrate in a direction crossing the isolation regions, a capping layer configured to define air gaps positioned higher than an upper surface of the semiconductor substrate in the isolation regions.
    Type: Application
    Filed: December 14, 2012
    Publication date: February 13, 2014
    Applicant: SK HYNIX INC.
    Inventors: Tae Kyung KIM, Jung Myoung SHIM, Myung Kyu AHN, Sung Soon KIM, Woo Duck JUNG