SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The semiconductor memory device includes a semiconductor substrate in which isolation regions and active regions are defined, gate lines formed on the semiconductor substrate in a direction crossing the isolation regions, a capping layer configured to define air gaps positioned higher than an upper surface of the semiconductor substrate in the isolation regions.
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This application is based on and claims priority from Korean Patent Application No. 10-2012-0086915 filed on Aug. 8, 2012, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
BACKGROUND1. Field
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device including an air gap and a method of manufacturing the semiconductor memory device.
2. Discussion of Related Art
A semiconductor memory device includes a plurality of memory cells for storing data and devices for various operations. High-density integration of the semiconductor memory device has been demanded for large capacity and light weight. Especially, areas of the memory cells occupied in a semiconductor chip is very wide, so that a decrease in sizes of and intervals between the memory cells has continuously become an issue.
In a NAND flash memory device, the memory cells are arranged in the unit of a string, a space between the strings, i.e. an isolation region, is filled with a device separation film formed of an insulating material. The device separation film serves to block an electrical influence, i.e. interference, between adjacent strings.
However, as the integration of the semiconductor memory devices is increased, there is a limit in blocking the interference between the strings by the device separation film formed of the insulating material, so that reliability of the semiconductor memory device may deteriorate.
SUMMARYThe present invention has been made in an effort to provide a semiconductor memory device capable of suppressing interference between the semiconductor memory devices and a method of is manufacturing the semiconductor memory device. An exemplary semiconductor memory device, includes a semiconductor substrate in which isolation regions and active regions are defined, gate lines formed on the semiconductor substrate in a direction crossing the isolation regions, a capping layer configured to define air gaps positioned higher than an upper surface of the semiconductor substrate in the isolation regions. An exemplary semiconductor memory device includes a semiconductor substrate in which an isolation region and an active region are defined, a tunnel insulation layer, a floating gate, a capping layer, a dielectric layer, and a control gate formed over the semiconductor substrate of the active region, a trench formed in the semiconductor substrate of the isolation region, and an air gap formed inside the trench, where the capping layer defines an upper surface of the air gap and where the capping layer is positioned higher than a surface of the semiconductor substrate.
A method of forming an exemplary semiconductor memory device includes forming a tunnel insulation layer and a floating gate on a semiconductor substrate of an active region, forming a trench in the semiconductor substrate of an isolation region, forming, in the trench, a sacrificial layer having an upper surface positioned higher than a surface of the semiconductor substrate, forming a capping layer over the sacrificial layer, and forming an air gap by removing the sacrificial layer without removing the capping layer.
An exemplary semiconductor memory device includes a plurality of gate lines formed on a semiconductor substrate, and a plurality of capping layers formed between the gate lines, wherein the capping layers define a plurality of air gaps between the gate lines.
A method of forming an exemplary semiconductor memory device includes forming a plurality of gate lines on a semiconductor substrate; alternately forming sacrificial layers and capping layers on the semiconductor substrate between the gate lines and forming a plurality of air, defined by the capping layers, between the gate lines by removing the sacrificial layers.
According to the embodiment of the present invention, the air gap is formed between the semiconductor memory devices, thereby suppressing interference between the semiconductor memory devices.
Further, in the method of forming the air gap, it is possible to form the air gap with a desired size at a desired position by using the sacrificial layer and the capping layer. Accordingly, a position at which interference is minimized is found through a simulation and the air gap is formed at a corresponding position, thereby improving reliability of the semiconductor memory device.
Further, it is possible to form the plurality of air gaps by is forming the plurality of capping layers between the gate lines. Accordingly, it is simultaneously possible to minimize interference between the gate lines by the plurality of air gaps and to prevent the gate lines from leaning by the plurality of capping layers.
The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects and features described above, further aspects and features will become apparent by reference to the drawings and the following detailed description.
The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail embodiments thereof with reference to the attached drawings in which:
Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings in detail. However, the present invention is not limited to an embodiment disclosed below and may be implemented in various forms and the scope of the present invention is not limited to the following embodiments. Rather, the embodiment is provided to more sincerely and fully disclose the present invention and to completely transfer the spirit of the present invention to those skilled in the art to which the present invention pertains, and the scope of the present invention should be understood by the claims of the present invention.
Referring to
A trench 107 is formed by etching the first conductive layer 105, the tunnel insulation layer 103, and the semiconductor substrate 101 of the isolation region. For example, although it is not illustrated in the drawing, the trench 107 may be formed by forming a mask pattern (not shown) in which the isolation region is opened on the first conductive layer 105 and sequentially etching the first conductive layer 105, the tunnel insulation layer 103, and the semiconductor substrate 101 exposed through the mask pattern (not shown). The mask pattern (not shown) may be removed after forming the trench 107.
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When the capping layer 113 is formed by the ALD method, step coverage may be improved and it is easy to form the capping layer 113 with a uniform thickness. A thickness of the capping layer 113 may be adjusted based on the specific memory device. In order to easily remove the sacrificial layer 111 (during a subsequent removal process), the capping layer 113 may have a thickness of about 5 Å to about 50 Å.
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Next, gate lines are arranged in a direction crossing the isolation region by performing a patterning process. That is, each of the gate lines may include the tunnel insulation layer 103, the first conductive layer 105, the capping layer 113, the dielectric layer 117, and the second conductive layer 119 stacked on the semiconductor substrate.
Referring to
A trench 207 is formed by etching the first conductive layer 205, the tunnel insulation layer 203, and the semiconductor substrate 201 of the isolation region. For example, although it is not illustrated in the drawing, the trench 207 may be formed by forming a mask pattern (not shown) in which the isolation region is opened on the first conductive layer 205 and sequentially etching the first conductive layer 205, the tunnel insulation layer 203, and the semiconductor substrate 201 exposed through the mask pattern (not shown). The mask pattern (not shown) may be removed after forming the trench 207.
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In this case, the etching process is performed with an etchant having a greater etching selectivity for the lower insulation layer 211 than for the liner insulation layer 209. That is, an etching speed of the lower insulation layer 211 is faster than an etching speed of the liner insulation layer.
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Next, gate lines are arranged in a direction crossing the isolation region are formed by performing a patterning process. That each of the gate lines may include the tunnel insulation layer 203, the first conductive layer 205, the capping layer 215, the dielectric layer 219, and the second conductive layer 221 stacked on the semiconductor substrate.
Referring to
As described above, a difference of interference is generated according to a position and a structure of the air gap, and a test is result of the interference difference will be described below.
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As can be seen from the graph of
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In
As described, it is possible to decrease interference between active regions by forming the air gap. Especially, when the air gap is formed within the isolation region, the interference may be effectively decreased as the upper surface of the air gap is higher than the is semiconductor substrate in the active region and is close to the width of the isolation region.
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In
As described above, an exemplary embodiment has been disclosed in the drawings and the specification. The specific terms used herein are for purposes of illustration, and do not limit the scope of the present invention recited in the claims. Accordingly, those skilled in the art will appreciate that various modifications and other equivalent examples may be made without departing from the scope and spirit of the present disclosure. Therefore, the sole technical protection scope of the present invention will be defined by the technical spirit of the accompanying claims.
Claims
1. A semiconductor memory device, comprising:
- a semiconductor substrate in which isolation regions and active regions are defined;
- gate lines formed on the semiconductor substrate in a direction crossing the isolation regions; and
- a capping layer configured to define air gaps positioned higher than an upper surface of the semiconductor substrate in the isolation regions.
2. The semiconductor memory device of claim 1, where the air gaps are formed in trenches defined in the isolation regions of the semiconductor substrate.
3. The semiconductor memory device of claim 1, where the capping layer is higher than the upper surface of the semiconductor substrate in the active regions by about 50 Å to about 150 Å.
4. The semiconductor memory device of claim 2, where the air gap has a same width as a width of the isolation region.
5. The semiconductor memory device of claim 2, further comprising:
- a liner insulation layer formed over a surface of the trenches, where a width of the air gap is a same width as a width of the trenches having the liner isolation layer.
6. The semiconductor memory device of claim 1, further comprising:
- a lower insulation layer to define a lower portion of the air gap in the isolation regions.
7. The semiconductor memory device of claim 6, where the lower insulation layer is formed of a flowable material.
8. The semiconductor memory device of claim 7, where the flowable material is a polisilazane (PSZ).
9. The semiconductor memory device of claim 6, where an upper surface of the lower insulation layer is lower than an upper surface of the semiconductor substrate of the active regions by about 100 Å to about 400 Å.
10. The semiconductor memory device of claim 1, where the capping layer is formed of a non-porous material.
11. The semiconductor memory device of claim 10, where the non-porous material includes a silicon dioxide (SiO2), a silicon nitride (SiN), a silicon oxynitride SiON, or a silicon carbide nitride (SiCN).
12. The semiconductor memory device of claim 1, where the capping layer is formed by atomic layer deposition (ALD).
13. The semiconductor memory device of claim 1, where the capping layer has a thickness of about 5 Å to about 50 Å.
14. The semiconductor memory device of claim 1, where each of the gate lines comprises a plurality of layers stacked on the semiconductor substrate, the plurality of layers including:
- a tunnel insulation layer,
- a first conductive layer for a floating gate,
- the capping layer, a dielectric layer, and
- a second conductive layer for a control gate.
15. The semiconductor memory device of claim 14, further comprising:
- an insulation layer formed between the capping layer and the dielectric layer in the isolation region.
16. The semiconductor memory device of claim 15, were the insulation layer and the capping layer support the upper portion of the air gap.
17. The semiconductor memory device of claim 15, where the insulation layer is formed of a flowable material.
18. The semiconductor memory device of claim 17, where the flowable material is a polisilazane (PSZ) layer.
19. A semiconductor memory device, comprising:
- a semiconductor substrate in which an isolation region and an active region are defined;
- a tunnel insulation layer, a floating gate, a capping layer, a dielectric layer, and a control gate formed over the semiconductor substrate of the active region;
- a trench formed in the semiconductor substrate of the isolation region; and
- an air gap formed inside the trench,
- where the capping layer defines an upper surface of the air gap and where the capping layer is positioned higher than a surface of the semiconductor substrate.
20. The semiconductor memory device of claim 19, where the capping layer is formed of a non-porous material.
21. The semiconductor memory device of claim 20, where the non-porous material includes a silicon dioxide (SiO2), a silicon nitride (SiN) a silicon oxynitride SiON, or a silicon carbide nitride (SiCN).
22. The semiconductor memory device of claim 19, where the capping layer has a thickness of about 5 Å to about 50 Å.
23. The semiconductor memory device of claim 19, further comprising:
- a lower insulation layer filling a lower portion of the trench, where the lower insulation layer is to define a lower surface of the air gap.
24. A method of manufacturing a semiconductor memory device, the method comprising:
- forming a tunnel insulation layer and a floating gate on a semiconductor substrate of an active region;
- forming a trench in the semiconductor substrate of an isolation region;
- forming, in the trench, a sacrificial layer having an upper surface positioned higher than a surface of the semiconductor substrate;
- forming a capping layer over the sacrificial layer; and
- forming an air gap by removing the sacrificial layer without removing the capping layer.
25. The method of claim 24, where the sacrificial layer is a flowable material containing carbon.
26. The method of claim 25, where sacrificial layer is a Spin-On-Carbon (SOC) layer or a photoresist (PR) layer.
27. The method of claim 25, further comprising:
- forming the sacrificial layer by spin coating.
28. The method of claim 24, where forming the sacrificial layer comprises:
- filling the trench with the sacrificial layer;
- solidifying the sacrificial layer by performing a heat treatment process; and
- etching the sacrificial layer so that an upper surface of the sacrificial layer is positioned higher than the surface of the semiconductor substrate.
29. The method of claim 28, where etching the sacrificial layer further comprises:
- etching the sacrificial layer so that the upper surface of the sacrificial layer is about 50 Å to about 150 Å higher than the surface of the semiconductor substrate.
30. The method of claim 24, further comprising:
- forming a lower insulation layer in a lower portion of the trench before forming the sacrificial layer in the trench.
31. The method of claim 30, where the lower insulation layer is formed of a flowable material.
32. The met hod of claim 31, where the flowable material is a polisilazane (PSZ).
33. The method of claim 30, where forming the lower insulation layer further comprises:
- solidifying the lower insulation layer by performing a heat treatment process; and
- etching the lower insulation layer so that an upper surface of the lower insulation layer is lower than the surface of the semiconductor substrate.
34. The method of claim 33, where etching the lower insulation layer further comprises:
- etching the lower insulation layer to be about 100 Å to about 400 Å lower than the surface of the semiconductor substrate.
35. The method of claim 24, where the capping layer is formed of a non-porous material.
36. The method of claim 35, where the non-porous material includes a silicon dioxide (SiO2), a silicon nitride (SiN), a silicon oxynitride SiON, or a silicon carbide nitride (SiCN).
37. The method of claim 24, where the capping layer is formed by atomic layer deposition (ALD) method at a low temperature.
38. The method of claim 37, where the low temperature includes a temperature range of about 50° C. to about 100° C.
39. The method of claim 24, where the capping layer has a thickness of about 5 Å to about 50 Å.
40. The method of claim 24, where removing the sacrificial layer further comprises:
- removing the sacrificial layer via plasma.
41. The method of claim 40, where the plasma is an oxygen, a nitrogen, or a hydrogen plasma.
42. The method of claim 24, further comprising;
- forming an insulation layer on the capping layer after forming the air gap; and
- etching the insulation layer so that only a portion of the insulation layer remains in the isolation region over the capping layer.
43. The method of claim 42, where the insulation layer is formed of a flowable material.
44. The method of claim 43, where the flowable material is a polisilazane (PSZ) layer.
45. A semiconductor memory device comprising;
- a plurality of gate lines formed on a semiconductor substrate; and
- a plurality of capping layers formed between the gate lines, wherein the capping layers define a plurality of air gaps between the gate lines.
46. The semiconductor memory device of claim 45, where the capping layers are formed of non porous materials.
47. The semiconductor memory device of claim 46, where the non-porous a materials include silicon dioxide (SiO2), a silicon nitride (SiN), a silicon oxynitride SiON, or a silicon carbide nitride (SiCN).
48. The semiconductor memory device of claim 45, where the plurality of capping layers are formed to have a thickness of about 5 Å to about 50 Å.
49. The semiconductor memory device of claim 45, where a width of an air gap, of the plurality of air gaps, formed at an upper portion of a gate line, of the plurality of gate lines, is narrower than a width of the air gap formed at a lower portion of the gate line.
50. A method of manufacturing a semiconductor memory is device, the method comprising:
- forming a plurality of gate lines on a semiconductor substrate;
- alternately forming sacrificial layers and capping layers on the semiconductor substrate between the gate lines and
- forming a plurality of air, defined by the capping layers, between the gate lines by removing the sacrificial layers.
51. The method of claim 50, where alternately forming the sacrificial layers and the capping layers further comprises:
- forming a sacrificial layer between the gate lines;
- solidifying the sacrificial layer;
- etching the sacrificial layer so that a remaining portion of the sacrificial layer has a predetermined thickness; and
- forming the capping layer over the remaining portion of the sacrificial layer.
52. The method of claim 50, where the sacrificial layer is formed of a flowable material containing carbon.
53. The method of claim 52, where the sacrificial layer is a Spin-On-Carbon (SOC) layer or a photoresist (PR) layer.
54. The method of claim 52, where the sacrificial layer is formed by spin coating.
55. The method of claim 50, where the capping layer is formed of a non-porous material.
56. The method of claim 50, where the non-porous layer material includes a silicon dioxide (SiO2), a silicon nitride (SiN), a silicon oxynitride SiON, or a silicon carbide nitride (SiCN).
57. The method of claim 50, where the capping layer is formed by atomic layer deposition (ALD) at a low temperature.
58. The method of claim 57, where the low temperature includes a temperature range of about 50° C. to about 100° C.
59. The method of claim 50, where the capping layer is has a is thickness of about 5 Å to about 50 Å.
Type: Application
Filed: Dec 14, 2012
Publication Date: Feb 13, 2014
Applicant: SK HYNIX INC. (Gyeonggi-do)
Inventors: Tae Kyung KIM (Chungcheongbuk-do), Jung Myoung SHIM (Gyeonggi-do), Myung Kyu AHN (Gyeonggi-do), Sung Soon KIM (Seoul), Woo Duck JUNG (Gyeonggi-do)
Application Number: 13/715,504
International Classification: H01L 29/06 (20060101); H01L 29/788 (20060101);