Patents by Inventor Jungtae Kwon
Jungtae Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11404096Abstract: Various implementations described herein refer to an integrated circuit having a memory cell array with a first number of rows and a second number of rows. The integrated circuit may include a first pre-decoder that receives a row address and selects a first row from the first number of rows based on the row address. The integrated circuit may include a second pre-decoder that receives the row address from the first pre-decoder and selects a second row from the second number of rows based on the row address received from the first pre-decoder. The integrated circuit may include a single row decoder that receives the row address and selects either the first row or the second row based on a row selection bit from the row address.Type: GrantFiled: December 7, 2018Date of Patent: August 2, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Jungtae Kwon, Nicolaas Klarinus Johannes Van Winkelhoff
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Patent number: 10839861Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.Type: GrantFiled: January 26, 2018Date of Patent: November 17, 2020Assignee: Arm LimitedInventors: Vivek Nautiyal, Satinderjit Singh, Abhishek B. Akkur, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Jungtae Kwon, Jitendra Dasani, Manoj Puthan Purayil
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Publication number: 20200185014Abstract: Various implementations described herein refer to an integrated circuit having a memory cell array with a first number of rows and a second number of rows. The integrated circuit may include a first pre-decoder that receives a row address and selects a first row from the first number of rows based on the row address. The integrated circuit may include a second pre-decoder that receives the row address from the first pre-decoder and selects a second row from the second number of rows based on the row address received from the first pre-decoder. The integrated circuit may include a single row decoder that receives the row address and selects either the first row or the second row based on a row selection bit from the row address.Type: ApplicationFiled: December 7, 2018Publication date: June 11, 2020Inventors: Andy Wangkun Chen, Jungtae Kwon, Nicolaas Klarinus Johannes VAN WINKELHOFF
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Publication number: 20190237111Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.Type: ApplicationFiled: January 26, 2018Publication date: August 1, 2019Inventors: Vivek Nautiyal, Satinderjit Singh, Abhishek B. Akkur, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Jungtae Kwon, Jitendra Dasani, Manoj Puthan Purayil
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Patent number: 9990972Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory bank having an array of memory cells that are accessible via a selected wordline and a pair of complementary bitlines. The integrated circuit may include a dummy wordline coupled to each of the pair of complementary bitlines via a pair of coupling capacitors. The dummy wordline may mimic the selected wordline. During transitions of the pair of complementary bitlines between first and second logic states, the dummy wordline may receive coupling capacitance from the pair of complementary bitlines via the pair of coupling capacitors.Type: GrantFiled: November 21, 2016Date of Patent: June 5, 2018Assignee: ARM LimitedInventors: Jungtae Kwon, Young Suk Kim
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Publication number: 20180144780Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory bank having an array of memory cells that are accessible via a selected wordline and a pair of complementary bitlines. The integrated circuit may include a dummy wordline coupled to each of the pair of complementary bitlines via a pair of coupling capacitors. The dummy wordline may mimic the selected wordline. During transitions of the pair of complementary bitlines between first and second logic states, the dummy wordline may receive coupling capacitance from the pair of complementary bitlines via the pair of coupling capacitors.Type: ApplicationFiled: November 21, 2016Publication date: May 24, 2018Inventors: Jungtae Kwon, Young Suk Kim
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Patent number: 9911510Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.Type: GrantFiled: October 7, 2016Date of Patent: March 6, 2018Assignee: ARM LimitedInventors: Jungtae Kwon, Young Suk Kim, Vivek Nautiyal, Pranay Prabhat, Fakhruddin Ali Bohra, Shri Sagar Dwivedi, Satinderjit Singh, Lalit Gupta
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Patent number: 9812179Abstract: Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.Type: GrantFiled: June 24, 2014Date of Patent: November 7, 2017Assignee: OVONYX MEMORY TECHNOLOGY, LLCInventors: Jungtae Kwon, David Kim, Sunil Bhardwaj
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Publication number: 20160004380Abstract: A method of performing a touch action in a touch-sensitive device is provided. The method includes detecting a shape of a contact area associated with a touch input provided on a touch screen, determining whether the detected shape is valid based on a predetermined criteria, detecting a gesture based on a movement of a validated shape, determining whether the detected gesture is valid by matching the detected gesture with one or more predefined gestures, and performing the touch action based on a determination that the detected gesture is valid and a determination that the detected shape is valid.Type: ApplicationFiled: July 6, 2015Publication date: January 7, 2016Inventors: Changjin KIM, Gunjan Prakash DEOTALE, Jungtae KWON, Niyas Ahmed SULTHAR THAJUDEEN, Niroj POKHREL, Rahul VAISH, Sreevatsa DWARAKA BHAMIDIPATI, Namyun KIM, Sanjay Dixit BHUVANAGIRI
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Patent number: 9093311Abstract: Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: GrantFiled: June 9, 2014Date of Patent: July 28, 2015Assignee: Micron Technology, Inc.Inventors: Michael A. Van Buskirk, Christian Caillat, Viktor I. Koldiaev, Jungtae Kwon, Pierre C. Fazan
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Publication number: 20150192989Abstract: An electronic device is provided. The electronic device includes a display for outputting an image, and a controller functionally connected to the display. The controller acquires a user input through at least one side surface of the display, determines grip information on the user input related to the electronic device based on the user input, and provides at least one of an application or a function corresponding to the grip information through the electronic device.Type: ApplicationFiled: January 7, 2015Publication date: July 9, 2015Inventors: Changjin KIM, Jungtae KWON, Namyun KIM, Dongsub KIM, Byeongjae KIM, Kwangtai KIM, Kwangmin KIL, Seongwoon KIM, Junghun KIM, Sejun SONG, Haejun AN, Yohan LEE, Hyerin CHO
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Publication number: 20150130867Abstract: An electronic device for adjusting voltages for each pixel includes an image processing unit to process a gray level corresponding to an image data, a gray data processing unit to determine voltages applied to each pixel of a display unit by using the gray level, and a power controller to control the voltage applied to each pixel of the display unit based on the determined voltage. Other embodiments including a method for adjusting voltages for each pixel are also disclosed.Type: ApplicationFiled: November 6, 2014Publication date: May 14, 2015Inventors: Dongyoul Park, Jungtae Kwon, Soohyung Kim, Jaemyung Baek, Jongkon Bae, Yongman Lee
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Publication number: 20150085586Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Applicant: ARM LIMITEDInventors: Bo ZHENG, Jungtae KWON, Gus YEUNG, Yew Keong CHONG
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Patent number: 8971133Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.Type: GrantFiled: September 26, 2013Date of Patent: March 3, 2015Assignee: ARM LimitedInventors: Bo Zheng, Jungtae Kwon, Gus Yeung, Yew Keong Chong
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Publication number: 20140307512Abstract: Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.Type: ApplicationFiled: June 24, 2014Publication date: October 16, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Jungtae KWON, David KIM, Sunil BHARDWAJ
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Publication number: 20140291763Abstract: Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: ApplicationFiled: June 9, 2014Publication date: October 2, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael A. VAN BUSKIRK, Christian CAILLAT, Viktor I. KOLDIAEV, Jungtae KWON, Pierre C. FAZAN
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Patent number: 8760906Abstract: Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.Type: GrantFiled: November 1, 2013Date of Patent: June 24, 2014Assignee: Micron Technology, Inc.Inventors: Jungtae Kwon, David Kim, Sunil Bhardwaj
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Patent number: 8748959Abstract: A semiconductor memory device is disclosed. In one particular exemplary embodiment, the semiconductor memory device includes a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation and a second barrier wall extending in the second orientation and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: GrantFiled: March 31, 2010Date of Patent: June 10, 2014Assignee: Micron Technology, Inc.Inventors: Michael A. Van Buskirk, Christian Caillat, Viktor I Koldiaev, Jungtae Kwon, Pierre C. Fazan
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Patent number: 8699289Abstract: Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.Type: GrantFiled: May 7, 2012Date of Patent: April 15, 2014Assignee: Micron Technology, Inc.Inventors: Jungtae Kwon, David Kim, Sunil Bhardwaj
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Publication number: 20140056090Abstract: Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.Type: ApplicationFiled: November 1, 2013Publication date: February 27, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Jungtae KWON, David KIM, Sunil BHARDWAJ