Patents by Inventor Jung Tsai

Jung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250141311
    Abstract: A motor driver using a spread spectrum mechanism for reducing electromagnetic interference is provided. The motor driver generates a plurality of waveforms in each of a plurality of on-time signals, and modulates frequencies of at least some of the plurality of waveforms in each of the plurality of on-time signals to be different from each other. The motor driver drives the motor according to the modulated plurality of on-time signals. As a result, electromagnetic wave energy emitted by the motor driver of the present disclosure is changed or dispersed such that the electromagnetic wave energy is not overly concentrated at a same frequency. Therefore, the motor driver of the present disclosure is prevented from emitting the accumulated and amplified electromagnetic wave energy to cause electromagnetic interference to the operations of other circuit components.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 1, 2025
    Inventor: MING-JUNG TSAI
  • Publication number: 20250132715
    Abstract: A motor driver for adjusting power based on a common voltage is provided. The motor driver includes a common voltage difference calculation circuit, a duty cycle determination circuit, a signal generator circuit, a control circuit, a driver circuit and an output stage circuit. The common voltage difference calculation circuit calculates a difference between the common voltage received by the output stage circuit and a threshold. The duty cycle determination circuit determines a duty cycle adjustment value according to the difference. The signal generator circuit adjusts a plurality of waveform signals according to the duty cycle adjustment value. The control circuit outputs control signals according to the plurality of waveform signals. The driver circuit outputs driving signals according to the control signals. The output stage circuit operates to drive the motor according to the common voltage and the driving signals.
    Type: Application
    Filed: January 29, 2024
    Publication date: April 24, 2025
    Inventors: MING-JUNG TSAI, HUAN-CHIEH CHOU
  • Publication number: 20250132273
    Abstract: An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.
    Type: Application
    Filed: January 2, 2025
    Publication date: April 24, 2025
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai
  • Publication number: 20250125237
    Abstract: Provided is an electronic package, in which a conductive structure and an encapsulation layer covering the conductive structure are arranged on one side of a carrier structure having a circuit layer, and an electronic component is arranged on the other side of the carrier structure. The rigidity of the carrier structure is increased by the encapsulation layer, and problems such as warpage or wavy deformations caused by increasing the volume of the electronic package due to functional requirements can be eliminated.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Inventors: Chih-Hsien Chiu, Ko-Wei Chang, Wen-Jung Tsai, Che-Wei Yu, Chia-Yang Chen
  • Patent number: 12263534
    Abstract: A laser beam shaping device includes a multi-zone structure lens and a focusing lens. The multi-zone structure lens includes a lens body and a refractive structure. The lens body has an incident plane and an emission plane, and one of the incident plane and the emission plane is furnished with the refractive structure. The light source passing through the refractive structure deviates and leaves the lens body via the emission plane. The light source passing through the lens body is divided into N sets of light beams. After the N sets of light beams penetrate through the focusing lens, N set of incident beams are formed to project the interface of the first material and the second material in an oblique inward manner with respect to the optical axis of the focusing lens. In additional, a laser processing system and a laser interlocking welding structure respectively are also provided.
    Type: Grant
    Filed: November 28, 2020
    Date of Patent: April 1, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yuan-Di Chen, Wu-Jung Tsai, Chia-Yu Hu
  • Patent number: 12260245
    Abstract: A method for deploying remote desktop gateways (RDGWs), a computer device, and a storage medium are provided. Application data of virtual machines (VMs) is obtained in RDGWs, the application data includes historical data and real-time data. A neural network is trained by using the historical data and a target classification model is obtained. The real-time data is inputted into the target classification model and a classification result of the real-time data is obtained. The VMs are deployed to a designated RDGW based on the classification result. The method allocates and deploys resources with greater efficiency.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: March 25, 2025
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Pei-Jung Tsai, Cheng-Ta Hsu
  • Publication number: 20250096153
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic component is disposed on a substrate and covered with an encapsulation layer, and a frame body is embedded in the encapsulation layer and protrudes from the substrate. Therefore, the frame body can disperse thermal stress, thereby preventing warping from occurring to the electronic package.
    Type: Application
    Filed: January 30, 2024
    Publication date: March 20, 2025
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chien-Cheng LIN, Chun-Chong CHIEN, Shih-Shiung KUO
  • Publication number: 20250087627
    Abstract: A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chia-Wei Wang, Yu-Tzu Chang
  • Publication number: 20250072636
    Abstract: An adjustable pillow has: a lower member, an upper member, and a lifting mechanism; the lower member having a neck supporting section at one end and an assembly space adjacent to the neck supporting section, the upper member having an assembly protrusion and a head supporting section extending from the assembly protrusion; wherein the assembly protrusion is capable of being correspondingly disposed in the assembly space such that the head supporting section is lower than the neck supporting section, and the assembly protrusion further comprises an accepting space at a bottom side for accepting the lifting mechanism for mounting between the lower member and the upper member.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 6, 2025
    Inventor: Chun-Jung Tsai
  • Publication number: 20250060676
    Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
  • Patent number: 12224255
    Abstract: An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.
    Type: Grant
    Filed: March 18, 2024
    Date of Patent: February 11, 2025
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai
  • Publication number: 20250038061
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic component and a heat dissipation structure having an opening are arranged on a carrier structure, a heat sink is arranged in the opening and bonded to the electronic component, and the electronic component, the heat dissipation structure and the heat sink are covered with an encapsulation layer, such that the heat sink can be arranged according to a heat source of a specific part of the electronic component so as to effectively dissipate heat.
    Type: Application
    Filed: January 12, 2024
    Publication date: January 30, 2025
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chia-Yang CHEN, Chien-Ming CHANG, Po-Hsin TSAI
  • Patent number: 12211776
    Abstract: Provided is an electronic package, in which a conductive structure and an encapsulation layer covering the conductive structure are arranged on one side of a carrier structure having a circuit layer, and an electronic component is arranged on the other side of the carrier structure. The rigidity of the carrier structure is increased by the encapsulation layer, and problems such as warpage or wavy deformations caused by increasing the volume of the electronic package due to functional requirements can be eliminated.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: January 28, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Ko-Wei Chang, Wen-Jung Tsai, Che-Wei Yu, Chia-Yang Chen
  • Publication number: 20250029946
    Abstract: A package structure includes an integrated circuit die and an encapsulant laterally encapsulating the integrated circuit die. The integrated circuit die includes a semiconductor substrate, an interconnection structure, a testing pad, a dummy post, a conductive post, and a protection layer. The interconnection structure is disposed on the semiconductor substrate. The testing pad is disposed on the interconnection structure. The dummy post is disposed on the testing pad. The conductive post is aside the dummy post. The protection layer is disposed between the conductive post and the dummy post.
    Type: Application
    Filed: October 3, 2024
    Publication date: January 23, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
  • Publication number: 20250022809
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, then a cladding layer is formed to cover the electronic element, and a shielding layer is formed on the cladding layer to cover the electronic element. The cladding layer is bonded to a shielding structure, and the shielding structure is located between the shielding layer and the electronic element, so as to prevent the electronic element from being subjected to external electromagnetic interference via multiple shielding mechanisms of the shielding structure and the shielding layer.
    Type: Application
    Filed: October 12, 2023
    Publication date: January 16, 2025
    Inventors: Wen-Jung TSAI, Chih-Hsien CHIU, Chien-Cheng LIN, Shao-Tzu TANG, Ko-Wei CHANG
  • Patent number: 12186240
    Abstract: The present invention provides an inpatient unit of modular design, built of recycled materials and environmentally friendly materials, allowing reconfiguration, redeployment and quick assembly, preventing indoor air from leaking, applicable to epidemic prevention and treating special patients, with high structural strength, lower cost and good environmental benefit.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: January 7, 2025
    Assignee: FU JEN CATHOLIC UNIVERSITY HOSPITAL, FU JEN CATHOLIC UNIVERSITY
    Inventors: Han-Sun Chiang, Ching-Chuan Jiang, Heng-Tai Chao, Wei-Lun Liu, Yi-Jen Jiang, Shiau-Jiun Lai, Heng-Lang Lin, Po-Jui Yu, Chin-Yu Hsieh, Chia-Jung Tsai, Yu-Hsuan Wu
  • Patent number: 12176321
    Abstract: A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chia-Wei Wang, Yu-Tzu Chang
  • Publication number: 20240421023
    Abstract: An electronic package is provided, in which an electronic element and a heat dissipation member are disposed on different areas of a carrier structure having a heat dissipation layer, where the electronic element is covered by an encapsulation layer, and the heat dissipation member is thermally connected to the electronic element via the heat dissipation layer, so that the heat energy generated by the electronic element can be prevented from conducting into the encapsulation layer during the heat dissipation process, such that the problem of overheating around the electronic element can be avoided.
    Type: Application
    Filed: September 12, 2023
    Publication date: December 19, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chin-Chiang HE, Wan-Chin CHUNG, Che-Wei YU
  • Patent number: 12165985
    Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Hung-Jui Kuo, Chung-Shi Liu, Han-Ping Pu, Ting-Chu Ko
  • Patent number: D1066740
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: March 11, 2025
    Assignee: AI NOSE CORPORATION
    Inventors: Chia-Pin Huang, Tzu-Ting Weng, Yu-Hsuan Liao, Chun-Hsien Tsai, Ting-Chuan Lee, Chun-Jung Tsai