Patents by Inventor Jung Tsai

Jung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12164232
    Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
  • Publication number: 20240398901
    Abstract: The present application provides a process for manufacturing an orally disintegrating tablet (ODT) comprising a cytokine as an active pharmaceutical ingredient comprising: acidifying an excipient, conducting a first granulation step of the acidified excipient to obtain acidic powders, and conducting a second granulation step by mixing the acidic powders and the cytokine to obtain granules containing the cytokine. The present application also provides an ODT manufactured by the process.
    Type: Application
    Filed: June 4, 2024
    Publication date: December 5, 2024
    Applicant: AINOS INC. TAIWAN BRANCH (USA)
    Inventors: Tsung-Fu YU, Yi-Yu TIEN, Chun-Hsien TSAI, Ting-Chuan LEE, Chun-Jung TSAI
  • Patent number: 12151452
    Abstract: The present invention relates to a composite laminate plate, a housing and a mobile communication device. The composite laminate includes a top metal layer with a through hole and an array antenna, and an area ratio of the array antenna to the through hole meets a specific range, thereby enhancing wave transmissivity of a millimeter wave. Moreover, the composite laminate has a specific material structure, such that it has good mechanical properties and low density. The housing and the mobile communication device made by the composite laminate have advantages of metallic texture, high signal intensity and excellent effect for light weight tendency.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: November 26, 2024
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Yen-Lin Huang, Pei-Jung Tsai, Li-De Wang, Chun-Chieh Wang
  • Publication number: 20240387392
    Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Hung-Jui Kuo, Chung-Shi Liu, Han-Ping Pu, Ting-Chu Ko
  • Publication number: 20240387789
    Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chen-Hua Yu, Keng-Han Lin, Hung-Jui Kuo, Hui-Jung Tsai
  • Publication number: 20240387450
    Abstract: A redistribution structure includes a first dielectric layer, a second dielectric layer, and a first metallization pattern. The second dielectric layer is located on the first dielectric layer. The first metallization pattern is located between the first dielectric layer and the second dielectric layer. The first metallization pattern includes a first seed layer and a first conductive material on the first seed layer to form a first conductive via, a first conductive line, and a second conductive via. The first conductive via is located in the first dielectric layer. The first conductive line is located in the second dielectric layer, and between the first conductive via and the second conductive via. The second conductive via is located on the first conductive line and in the second dielectric layer.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chia-Wei Wang, Yu-Tzu Chang
  • Patent number: 12148732
    Abstract: A method of forming a redistribution structure includes providing a dielectric layer. The dielectric layer is patterned to form a plurality of via openings. A seed layer is formed on the dielectric layer and filling in the plurality of via openings. A patterned conductive layer is formed a on the seed layer, wherein a portion of the seed layer is exposed by the patterned conductive layer. The portion of the seed layer is removed by using an etching solution, thereby forming a plurality of conductive lines and a plurality of vias. During the removing the portion of the seed layer, an etch rate of the patterned conductive layer is less than an etch rate of the seed layer.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chia-Wei Wang, Yu-Tzu Chang
  • Publication number: 20240358290
    Abstract: A device for detecting or identifying diseases or disorders in a human subject by collecting biological sample from the human subject comprises a pump unit, a first unit, a second unit, a gas permeable filter, and a collector. The first unit comprises a first chamber and a gas sensor unit. The second unit comprises a second chamber, an outlet portion and an inlet portion. The gas permeable filter is disposed in an upstream region of the second chamber. The collector is disposed in a downstream region of the second chamber. The pump unit is configured, when activated, to create a negative pressure in a gas flow pathway provided between the first chamber and second chamber through the outlet portion, thereby allowing an ambient gas stream forcedly flows from an exterior through the inlet portion into the second chamber and the first chamber.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Chia-Nan LIAO, Chun-Hsien TSAI, Ting-Chuan LEE, Chun-Jung TSAI
  • Publication number: 20240364001
    Abstract: An antenna module is provided with a plurality of antenna structures and a shielding structure arranged on a plate body, and the shielding structure is located between two adjacent antenna structures, where the shielding structure includes a concave portion formed on the plate body and a dielectric material formed between the concave portion and the antenna structure to generate different impedance characteristics, thereby improving the antenna isolation.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shao-Tzu TANG, Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Chia-Chu LAI
  • Publication number: 20240363450
    Abstract: Provided is a method of detecting photoresist scums and photoresist residues. A carrier is provided. The carrier has a photoresist layer with opening patterns therein. A plasma etching process is performed to the opening patterns of the photoresist layer. Charges are injected to the opening patterns of the photoresist layer. Whether a photoresist scum or residue is present in at least one of the opening patterns is detected.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chih Wang
  • Patent number: 12132023
    Abstract: An integrated circuit includes a semiconductor substrate, contact pads, testing pads, conductive posts, dummy posts, and a protection layer. The contact pads and the testing pads are distributed over the semiconductor substrate. The conductive posts are disposed on the contact pads. The dummy posts are disposed on the testing pads and are electrically floating. The protection layer covers the conductive posts and the dummy posts. A distance between top surfaces of the conductive posts and a top surface of the protection layer is smaller than a distance between top surfaces of the dummy posts and the top surface of the protection layer.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
  • Patent number: 12105006
    Abstract: A gas detection system for gynecological disease detection and a detection method using the same are provided. The gas detection system is configured to detect an analyte from a female vagina and includes a main body, a sleeve, a detector, a pump, and a controller. The main body includes a body portion and a head portion having an intake channel. The body portion includes a detection chamber and an exhaust channel. The detector includes at least one sensor configured to detect at least one target of the analyte and produce at least one detection signal. The pump is communicated with the detection chamber and the exhaust channel. The controller includes a processing unit and a first communication unit. The processing unit receives the at least one detection signal and controls the first communication unit to send the at least one detection signal.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: October 1, 2024
    Assignee: AINOS, INC.
    Inventors: Chia-Nan Liao, Chia-Pin Huang, Tzu-Ting Weng, Yu-Hsuan Liao, Chun-Hsien Tsai, Ting-Chuan Lee, Chun-Jung Tsai
  • Publication number: 20240321784
    Abstract: An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.
    Type: Application
    Filed: March 18, 2024
    Publication date: September 26, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai
  • Publication number: 20240321765
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Publication number: 20240321769
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a plurality of electronic components and a shielding part are disposed on a carrier structure, the shielding part is located between two of the electronic components, and the plurality of electronic components and the shielding part are covered by an encapsulating layer, where a surface of the shielding part has a protruding portion. Therefore, a periphery surface of the shielding part is a non-straight surface, so as to prevent the reflection of electromagnetic waves in the encapsulating layer from interfering with the signal transmission of the electronic components.
    Type: Application
    Filed: July 12, 2023
    Publication date: September 26, 2024
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Wan-Chin CHUNG, Chih-Chiang HE, Chun-Chong CHIEN
  • Patent number: 12100641
    Abstract: An electronic package is provided, which includes a plurality of electronic components encapsulated by an encapsulation layer. A spacer is defined in the encapsulation layer and located between at least two adjacent electronic components of the plurality of electronic components, and a recess is formed in the spacer and used as a thermal insulation area. With the design of the thermal insulation area, the plurality of electronic components can be effectively thermally insulated from one another to prevent heat generated by one electronic component of high power from being conducted to another electronic component of low power that would thermally affect the operation of the low-power electronic component. A method for manufacturing the electronic package is also provided.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: September 24, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Siang-Yu Lin, Wen-Jung Tsai, Chia-Yang Chen, Chien-Cheng Lin
  • Publication number: 20240304542
    Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.
    Type: Application
    Filed: May 16, 2024
    Publication date: September 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
  • Publication number: 20240297126
    Abstract: An electronic package is provided in which an electronic component is arranged on a wiring structure and covered with a packaging layer, and a frame body that does not contact the wiring structure is embedded in the packaging layer. Therefore, thermal stress is dispersed through the frame body to avoid warpage of the electronic package, so as to facilitate the arrangement of other electronic components around the electronic component.
    Type: Application
    Filed: May 10, 2024
    Publication date: September 5, 2024
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chien-Cheng LIN, Ko-Wei CHANG, Yu-Wei YEH, Shun-Yu CHIEN, Chia-Yang CHEN
  • Patent number: 12080609
    Abstract: Provided is a method of detecting photoresist scums and photoresist residues. A carrier is provided. The carrier has a photoresist layer with opening patterns therein. A plasma etching process is performed to the opening patterns of the photoresist layer. Charges are injected to the opening patterns of the photoresist layer. Whether a photoresist scum or residue is present in at least one of the opening patterns is detected.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: September 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chih Wang
  • Publication number: 20240290728
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a cover is disposed on a carrier structure having an electronic element, and the electronic element is covered by the cover. A magnetic conductive member is arranged between the cover and the electronic element, and an air gap is formed between the magnetic conductive member and the cover to enhance the shielding effect of the electronic package.
    Type: Application
    Filed: June 14, 2023
    Publication date: August 29, 2024
    Inventors: Wen-Jung TSAI, Chih-Hsien CHIU, Chien-Cheng LIN, Ming-Fan TSAI, Cheng-You JENG, Hui-Jing CHANG