Abstract: Provided is a display device. A display device includes a display area and a buffer area disposed around the display area, a pixel electrode disposed on a substrate and in the display area, a bank covering an edge of the pixel electrode, light emitting elements disposed on the pixel electrode and extending in a thickness direction of the substrate, and a buffer disposed on the substrate and in the buffer area. The bank and the buffer are disposed on a same layer.

Abstract: The present invention relates to a light irradiation apparatus including: a body part, base parts coupled to the body part, light irradiators coupled to the corresponding base part to irradiate light on a user's body, and position adjustors for adjusting the light irradiators in position and having one or more actuators controlled by a computing device, wherein the one or more actuators adjust the light irradiators in position so that the positions of the light irradiators correspond to the user's body on which the light is irradiated.

Abstract: The present invention relates to an integrated connector and a heat exchanger including the same, in which a connector main body is formed by pressing one pipe, a cap is press-fitted into the connector main body, such that the integrated connector is formed so that an interior of the connector main body is blocked by the cap. Therefore, the number of components used to manufacture a connector, which connects and securely couples a header tank and a gas-liquid separator, may be reduced, the integrated connector may be easily manufactured, and a brazing defect may be reduced at portions where the integrated connector is joined to the header tank and the gas-liquid separator of the heat exchanger.

Abstract: The disclosure relates to a display device including an oxide semiconductor pattern. The disclosure provides a driving thin film transistor and a switching thin film transistor using an oxide semiconductor pattern as an active layer. Each of the driving thin film transistor and the switching thin film transistor includes a light shielding pattern. The light shielding pattern includes a semiconductor material layer doped with P-type impurity ions. By virtue of the light shielding pattern including the semiconductor material layer, each of the driving thin film transistor and the switching thin film transistor exhibits an increase in threshold voltage and, as such, freedom of circuit design is secured.

Abstract: A display apparatus is provided. The display apparatus may include a light-emitting device and a pixel driving circuit electrically connected to the light-emitting device. The pixel driving circuit may supply a driving current corresponding to a data signal to the light-emitting device according to a gate signal. For example, the pixel driving circuit may include at least one thin film transistor. The thin film transistor may include an active pattern comprising an oxide semiconductor. A source region of the active pattern overlaps a source semiconductor pattern, and a drain region of the active pattern overlaps a drain semiconductor pattern. The source semiconductor pattern and the drain semiconductor pattern may include n-type impurities. A channel region of the active pattern may be outside the source semiconductor pattern and the drain semiconductor pattern. Thus, in the display apparatus, reliability of the pixel driving circuit may be improved.

Abstract: The disclosure provides an array substrate of a thin film transistor including an oxide semiconductor pattern, and a display device using the same. The thin film transistor array substrate includes a substrate including an active area and a non-active area disposed around the active area, and a first thin film transistor disposed on the substrate. The first thin film transistor includes a first oxide semiconductor pattern disposed on the substrate, a first gate electrode disposed under the first oxide semiconductor pattern while overlapping with the first oxide semiconductor pattern, a first source electrode and a first drain electrode disposed on the first oxide semiconductor pattern and connected to the first oxide semiconductor pattern, and a first light shielding pattern disposed over the first oxide semiconductor pattern and electrically connected to one of the first source electrode and the first drain electrode while overlapping with the first oxide semiconductor pattern.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a plurality of lower lines disposed over a substrate and extending in a first direction; a plurality of upper lines disposed over the lower lines and extending in a second direction crossing the first direction; a plurality of memory cells disposed between the lower lines and the upper lines and overlapping intersection regions of the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction.

Abstract: The present disclosure relates to a power conversion device and a control method thereof and, more specifically, to a power conversion device which may protect a switching element when performing stopping of driving, and a control method thereof. A power conversion device according to an embodiment of the present disclosure comprises a pulse width modulation (PWM) controller for outputting, to a gate driver, a first pulse width modulation signal for controlling a first switching element, a second pulse width modulation signal for controlling a second switching element, a third pulse width modulation signal for controlling a third switching element, and a fourth pulse width modulation signal for controlling a fourth switching element.

Abstract: A method for manufacturing a semiconductor device may include: forming a plurality of stacked structures over a substrate, the substrate including one or more peripheral circuit regions and one or more cell regions, the stacked structures including first conductive lines and initial memory cells respectively disposed over the first conductive lines, each of the stacked structures extending in a first direction; forming a first insulating layer between the stacked structures; forming second conductive lines over the stacked structures and the first insulating layer, each of the second conductive lines extending in a second direction; forming memory cells by etching the initial memory cells exposed by the second conductive lines; forming a second insulating layer between the second conductive lines and between the memory cells; and removing the first conductive lines, the memory cells, and the second conductive lines in the peripheral circuit regions.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a plurality of lower lines disposed over a substrate and extending in a first direction; a plurality of upper lines disposed over the lower lines and extending in a second direction crossing the first direction; a plurality of memory cells disposed between the lower lines and the upper lines and overlapping intersection regions of the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a plurality of lower lines disposed over a substrate and extending in a first direction; a plurality of upper lines disposed over the lower lines and extending in a second direction crossing the first direction; a plurality of memory cells disposed between the lower lines and the upper lines and overlapping intersection regions of the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a plurality of lower lines disposed over a substrate and extending in a first direction; a plurality of upper lines disposed over the lower lines and extending in a second direction crossing the first direction; a plurality of memory cells disposed between the lower lines and the upper lines and overlapping intersection regions of the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a lower electrode disposed on the semiconductor substrate wherein an upper surface of the lower electrode has a recess, an interlayer insulating layer disposed on the semiconductor substrate and the lower electrode, the interlayer insulating layer including a variable resistive region exposing the upper surface of the lower electrode, and a variable resistive layer filled in the variable resistive region that contacts the recess of the lower electrode. The variable resistive layer is formed to have an increased width toward a top and a bottom thereof.

Abstract: A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof.

Abstract: A glass filler manufacturing process and product which enable the manufacture of dental composite and dental cement products having superior product stability and also having superior physical properties. The process makes use of barium glass filler and strontium glass filler, which have high-radiopacity properties but could not previously be used for dental composites and dental cement. By simply coating the surface of the barium glass or strontium glass filler with an oxide having acid-resistance properties, and then following with a heat-treatment process, a suitable dental composite can be produced.

Abstract: A semiconductor device includes a data storage layer formed over a semiconductor substrate in which a lower structure is formed, and an electrode structure formed on at least one side of the data storage layer over the semiconductor substrate. The electrode structure includes a metal pattern, and a graphene pattern formed over the metal pattern.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate in which a lower structure is formed, forming a phase-change material layer of a first state over the lower structure, transforming an upper region of the phase-change material layer of the first state into a phase-change material layer of a second state having an etch selectivity different from the phase-change material layer of the first state, removing the phase-change material layer of the second state, and forming an upper electrode over the phase-change material layer of the first state in which the phase-change material layer of the second state is removed.

Abstract: A resistive memory device may include a bottom structure, a memory cell structure disposed on the bottom structure, and a data storage material disposed to surround an outer sidewall of the memory cell structure.

Abstract: A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof.

Abstract: The present invention relates to a transparent memory for a transparent electronic device. The transparent memory includes: a lower transparent electrode layer that is sequentially formed on a transparent substrate, and a data storage region and an upper transparent layer which are made of at least one transparent resistance-variable material layer. The transparent resistance-variable material layer has switching characteristics as a result of the resistance variance caused by the application of a certain voltage between the lower and upper transparent electrode layers. An optical band gap of the transparent resistance-variable material layer is 3 eV or more, and transmittivity of the material layer for visible rays is 80% or more. The invention provides transparent and resistance-variable memory that: has very high transparency and switching characteristics depending on resistance variation at a low switching voltage, and can maintain the switching characteristics thereof after a long time elapses.