Patents by Inventor Jung-Yu Hsieh
Jung-Yu Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10816483Abstract: A reticle inspection system and related method are disclosed. The system includes a concave spherical mirror positioned adjacent a side of the reticle that is configured to reflect inspection light transmitted through the reticle back towards and through the reticle. A sensor is configured to create at least one of: a first inspection image representative of a circuit pattern of the reticle based on transmission of the inspection light through the first side of the reticle and a reflection thereof by the concave spherical mirror through the second side of the reticle, and a second inspection image representative of the circuit pattern of the reticle based on the reflection of the inspection light from the first side of the reticle. A controller is configured to identify a defect in the reticle based on at least one of the first inspection image and the second inspection image.Type: GrantFiled: December 27, 2018Date of Patent: October 27, 2020Assignee: GlobalFoundries Inc.Inventors: Jed H. Rankin, Guoxiang Ning, Paul W. Ackmann, Jung-Yu Hsieh, Ming Lei
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Publication number: 20200209166Abstract: A reticle inspection system and related method are disclosed. The system includes a concave spherical mirror positioned adjacent a side of the reticle that is configured to reflect inspection light transmitted through the reticle back towards and through the reticle. A sensor is configured to create at least one of: a first inspection image representative of a circuit pattern of the reticle based on transmission of the inspection light through the first side of the reticle and a reflection thereof by the concave spherical mirror through the second side of the reticle, and a second inspection image representative of the circuit pattern of the reticle based on the reflection of the inspection light from the first side of the reticle. A controller is configured to identify a defect in the reticle based on at least one of the first inspection image and the second inspection image.Type: ApplicationFiled: December 27, 2018Publication date: July 2, 2020Inventors: Jed H. Rankin, Guoxiang Ning, Paul W. Ackmann, Jung-Yu Hsieh, Ming Lei
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Patent number: 9368453Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.Type: GrantFiled: November 23, 2015Date of Patent: June 14, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Guoxiang Ning, Chan Seob Cho, Paul Ackmann, Jung Yu Hsieh, Hui Peng Koh
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Publication number: 20160079180Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.Type: ApplicationFiled: November 23, 2015Publication date: March 17, 2016Inventors: Guoxiang NING, Chan Seob CHO, Paul ACKMANN, Jung Yu HSIEH, Hui Peng KOH
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Patent number: 9252061Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.Type: GrantFiled: April 2, 2014Date of Patent: February 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Guoxiang Ning, Chan Seob Cho, Paul Ackmann, Jung Yu Hsieh, Hui Peng Koh
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Publication number: 20150287651Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.Type: ApplicationFiled: April 2, 2014Publication date: October 8, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Guoxiang NING, Chan Seob CHO, Paul ACKMANN, Jung Yu HSIEH, Hui Peng KOH
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Patent number: 8969205Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different in composition from the sidewall spacers, such as a flowable oxide. The mandrels are removed such that the sidewall spacers have vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a hard mask to pattern the SiN hard mask below.Type: GrantFiled: March 28, 2013Date of Patent: March 3, 2015Inventors: HongLiang Shen, Dae-Han Choi, Dae Geun Yang, Jung Yu Hsieh
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Publication number: 20140291735Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different in composition from the sidewall spacers, such as a flowable oxide. The mandrels are removed such that the sidewall spacers have vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a hard mask to pattern the SiN hard mask below.Type: ApplicationFiled: March 28, 2013Publication date: October 2, 2014Applicant: GLOBAL FOUNDRIES, Inc.Inventors: HongLiang Shen, Dae-Han Choi, Dae Geun Yang, Jung Yu Hsieh
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Patent number: 8581322Abstract: A method for making a nonvolatile memory device includes the following steps. A conductive structure is formed, wherein the conductive structure has a first top portion. The first top portion is converted into a second top portion having a domed surface.Type: GrantFiled: June 28, 2011Date of Patent: November 12, 2013Assignee: Macronix International Co., Ltd.Inventors: Chi-Pin Lu, Jung-Yu Hsieh, Ling-Wuu Yang
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Publication number: 20130001667Abstract: A method for making a nonvolatile memory device includes the following steps. A conductive structure is formed, wherein the conductive structure has a first top portion. The first top portion is converted into a second top portion having a domed surface.Type: ApplicationFiled: June 28, 2011Publication date: January 3, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chi-Pin Lu, Jung-Yu Hsieh, Ling-Wuu Yang
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Patent number: 8183618Abstract: A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.Type: GrantFiled: December 7, 2010Date of Patent: May 22, 2012Assignee: Macronix International Co., Ltd.Inventors: Yen-Hao Shih, Chi-Pin Lu, Jung-Yu Hsieh
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Patent number: 8106483Abstract: An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×105-3.38×109/cm3 through first and second annealing steps. The first annealing step is performed at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. The second annealing step is performed at a second temperature higher than the first temperature in the atmosphere.Type: GrantFiled: March 29, 2011Date of Patent: January 31, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Ling Chiang, Jung-Yu Hsieh, Ling-Wu Yang
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Patent number: 8026136Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm?2, and methods for forming such memory cells.Type: GrantFiled: December 26, 2007Date of Patent: September 27, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Yen-Hao Shih, Min-Ta Wu, Shih-Chin Lee, Jung-Yu Hsieh, Erh-Kun Lai, Kuang Yeu Hsieh
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Patent number: 8022466Abstract: Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.Type: GrantFiled: October 27, 2006Date of Patent: September 20, 2011Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Yen-Hao Shih, Tzu-Hsuan Hsu, Shih-Chih Lee, Jung-Yu Hsieh, Kuang-Yeu Hsieh
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Patent number: 8022465Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm?2, and methods for forming such memory cells.Type: GrantFiled: November 15, 2005Date of Patent: September 20, 2011Assignee: Macronrix International Co., Ltd.Inventors: Yen-Hao Shih, Min-Ta Wu, Shin-Chin Lee, Jung-Yu Hsieh, Erh-Kun Lai, Kuang Yeu Hsieh
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Publication number: 20110175203Abstract: An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×105-3.38×109/cm3 through first and second annealing steps. The first annealing step is performed at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. The second annealing step is performed at a second temperature higher than the first temperature in the atmosphere.Type: ApplicationFiled: March 29, 2011Publication date: July 21, 2011Applicant: MACRONIX International Co. Ltd.Inventors: CHUN-LING CHIANG, JUNG-YU HSIEH, LING-WU YANG
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Patent number: 7939432Abstract: A method of improving the intrinsic gettering ability of a wafer is described. A first annealing step is performed to the wafer at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. A second annealing step is performed to the wafer, at a second temperature higher than the first temperature, in the atmosphere.Type: GrantFiled: December 15, 2008Date of Patent: May 10, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Ling Chiang, Jung-Yu Hsieh, Ling-Wu Yang
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Publication number: 20110073937Abstract: A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yen-Hao Shih, Chi-Pin Lu, Jung-Yu Hsieh
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Patent number: 7863132Abstract: A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.Type: GrantFiled: June 20, 2006Date of Patent: January 4, 2011Assignee: Macronix International Co., Ltd.Inventors: Yen-Hao Shih, Chi-Pin Lu, Jung-Yu Hsieh
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Publication number: 20100210085Abstract: A method for fabricating a non-volatile memory of the invention includes providing a substrate, and a tunnel layer is formed on the substrate. A charge-trapping layer is formed on the tunnel layer using silane (SiH4), nitrous oxide (N2O), and ammonia (NH3) as a reactant gas. The charge-trapping layer has a refractive index greater than or equal to 1.49 but less than 1.96 at a wavelength of 633 nm. A top layer is formed on the charge-trapping layer. A gate is formed on the top layer.Type: ApplicationFiled: April 26, 2010Publication date: August 19, 2010Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jeng-Hwa Liao, Jung-Yu Hsieh, Ling-Wu Yang