Abstract: In a method for forming STI in a silicon substrate having a pad oxide over the substrate, a hard mask is formed over the pad oxide, the hard mask and the pad oxide are patterned to form an opening, the silicon substrate is etched through the opening to form a trench, a liner oxide is formed over the trench, an STI insulator is formed in the trench, and the hard mask and the pad oxide are removed. Before the formation of the liner oxide, a clean process is performed that comprises applying silicon-consuming solution to round the top corners of the trench.

Abstract: Roughly described, a floating gate memory cell is fabricated by forming an oxide-nitride dielectric layer above a floating gate of the memory cell and in an oxide growth region not above a floating gate. The nitride layer is removed in the oxide growth region using a mask that protects the nitride layer above the floating gate, and then the bottom oxide layer is removed in the oxide growth region using a wet etch that does not affect the nitride remaining above the floating gate. First and second oxide layers are then formed both above the floating gate and in the oxide growth region, to act as the top layer of ONO above the floating gate and as the gate oxide in the oxide growth region. One of the first and second oxide layers is formed using in-situ steam generation.

Abstract: A method of fabricating a semiconductor device includes providing a wafer substrate, forming a first oxide layer over the wafer substrate using a single wafer low pressure chemical vapor deposition oxidation process, forming a second oxide layer over the first oxide layer by a single wafer oxidation process, forming a nitride layer over the second oxide layer using a low temperature and pressure deposition process, and growing a top oxide layer over the nitride layer.

Abstract: A method of fabricating a semiconductor device includes providing a wafer substrate, forming a first oxide layer over the wafer substrate using a single wafer low pressure chemical vapor deposition oxidation process, forming a second oxide layer over the first oxide layer by a single wafer oxidation process, forming a nitride layer over the second oxide layer using a low temperature and pressure deposition process, and growing a top oxide layer over the nitride layer.

Abstract: A method of fabricating a flash memory. A tunneling dielectric layer and a conductive layer are formed on a substrate. The conductive layer is patterned to form a floating gate. A source/drain region is formed in the substrate between the floating gates. A gate dielectric layer is formed. The gate dielectric layer includes an oxide layer formed on the floating gate by in-situ steam generation (ISSG). A control gate is formed on the gate dielectric layer.

Abstract: A method of fabricating a semiconductor device is disclosed. A wafer substrate is provided. A first silicon oxide layer is formed over the wafer substrate. A nitride layer is formed over the first silicon oxide layer using a low temperature deposition process. A second silicon oxide layer is formed over the nitride layer. The low temperature process can form a nitride layer for an oxide-nitride-oxide (ONO) dielectric structure at about a temperature of 700° C. By such a process, an ONO dielectric structure can be formed using a low temperature deposition process, which can reduce the thickness of the ONO dielectric structure.

Abstract: A method of fabricating a semiconductor device is disclosed. A wafer substrate is provided. A first silicon oxide layer is formed over the wafer substrate. A nitride layer is formed over the first silicon oxide layer using a low temperature deposition process. A second silicon oxide layer is formed over the nitride layer. The low temperature process can form a nitride layer for an oxide-nitride-oxide (ONO) dielectric structure at about a temperature of 700° C. By such a process, an ONO dielectric structure can be formed using a low temperature deposition process, which can reduce the thickness of the ONO dielectric structure.

Abstract: The present invention provides a method for forming a silicon nitride spacer by using an atomic layer deposition (ALD) method. The procedure of the ALD is to use a first kind of excess gas as a reactant air and thus produce a first mono-layer solid phase of the first reactant air on the wafer. When the first chemical reaction is completed, the first excess air is drawn out, and then the second excess air is released to deposit a second mono-layer solid phase of the second reactant air on the first mono-layer solid phase. In this way, a whole deposited layer with a layer of the first mono-layer solid phase, a layer of the second mono-layer solid phase, and so on are stepwise formed on the wafer surface. The ALD method is a time consuming task in deposition process such as in the generation of 0.35 &mgr;m to 0.5 &mgr;m of VLSI ages. However, in the generation of 0.18 &mgr;m, 0.

Abstract: The present invention provides a method for forming a silicon nitride spacer by using an atomic layer deposition (ALD) method. The procedure of the ALD is to use a first kind of excess gas as a reactant air and thus produce a first mono-layer solid phase of the first reactant air on the wafer. When the first chemical reaction is completed, the first excess air is drawn out, and then the second excess air is released to deposit a second mono-layer solid phase of the second reactant air on the first mono-layer solid phase. In this way, a whole deposited layer with a layer of the first mono-layer solid phase, a layer of the second mono-layer solid phase, and so on are stepwise formed on the wafer surface. The ALD method is a time consuming task in deposition process such as in the generation of 0.35 &mgr;m to 0.5 &mgr;m of VLSI ages. However, in the generation of 0.18 &mgr;m, 0.

Abstract: A method for forming an ONO structure in one chamber. The method at least includes the following steps. First of all, a substrate is provided. Then, a first oxide layer is formed on the substrate. Next, a first buffer layer is formed on the first oxide layer, and a silicon nitride layer is formed on the first buffer layer. Next, a second buffer layer is formed on the silicon nitride layer. Finally, a second oxide layer is formed on the second buffer layer.

Abstract: An overlay mark for concurrently monitoring alignment accuracy, focus, leveling and astigmatism and a method of application thereof are disclosed. The overlay mark comprises four inner bars and four outer bars formed at the corners of exposure areas. The inner bar has a sawtooth area and a bar-shaped area, and the outer bar is a fore-layer etched pattern. Both the inner bars and the outer bars are formed into rectangles, and each bar is one side of a rectangle and none of the sides are connected. The sawtooth areas of the inner bars disposed on opposite sides are located at a same position. The rectangle formed by the outer bars encloses the rectangle formed by the inner bars. During the monitoring process, a testing beam scans across a scan area being divided into two areas, i.e., one being the outer bars and the sawtooth area of the inner bars, and the other one being the outer bars and the bar-shaped area of the inner bars.

Abstract: A flash memory structure which includes a tunneling oxide layer, a floating gate, a dielectric stacked layer, a control gate and a source/drain region. The dielectric stacked layer is formed by successively stacking a first oxide layer, a dielectric layer made of a high dielectric constant material and a second oxide layer, and is installed between the floating gate and the control gate. The floating gate is formed on the tunneling oxide layer. The control gate is formed on the dielectric stacked layer. The source/drain region is installed within the substrate on the two sides of the floating gate.

Abstract: A structure of a flash memory is provided. The flash memory has a charge trapping layer, a gate and a source/drain region, wherein the charge trapping layer is formed by stacking in sequence a first oxide layer, a dielectric layer of high dielectric constant material and a second oxide layer. The gate is arranged on the charge trapping layer, and the source/drain region is arranged at the two lateral sides of the substrate.

Abstract: A method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process is disclosed. After forming a dielectric layer on the semiconductor substrate and smoothing the dielectric layer as an inner dielectric layer, a stop layer of undoped silicon dioxide, organ spin on glass, or silicon oxygen nitride are coated thereon. After process of plug lithographic and etching, a barrier layer of tungsten plug and metal tungsten are deposited sequentially. Finally, the surplus tungsten metal layer on the surface of a dielectric layer is removed by chemical mechanic grinding process until the stop layer is exposed. In the present invention, the stop layer is used to repair the scratches or defects generated from the smoothness in the chemical mechanic grinding process. Furthermore, in the tungsten chemical mechanic grinding process, it can assure that the inner dielectric layer will not be ground so that the object of low loss is achieved.