Abstract: A transistor structure including a substrate, a gate structure, first pocket doped regions, second pocket doped regions, and source/drain extension regions, and source/drain regions is provided. The gate structure is located on the substrate. The first pocket doped regions are located in the substrate aside the gate structure. A dopant of the first pocket doped region includes a group IVA element. The second pocket doped regions are located in the substrate aside the gate structure. A depth of the second pocket doped region is greater than a depth of the first pocket doped region. The source/drain extension regions are located in the first pocket doped regions. The source/drain regions are located in the substrate aside the gate structure. The source/drain extension region is located between the source/drain region and the gate structure.

Abstract: A transistor structure including a substrate, a gate structure, first pocket doped regions, second pocket doped regions, and source/drain extension regions, and source/drain regions is provided. The gate structure is located on the substrate. The first pocket doped regions are located in the substrate aside the gate structure. A dopant of the first pocket doped region includes a group IVA element. The second pocket doped regions are located in the substrate aside the gate structure. A depth of the second pocket doped region is greater than a depth of the first pocket doped region. The source/drain extension regions are located in the first pocket doped regions. The source/drain regions are located in the substrate aside the gate structure. The source/drain extension region is located between the source/drain region and the gate structure.

Abstract: Provided is a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a periphery region and an array region. The first isolation structures are located in the substrate of the periphery region. The second isolation structures are located in the substrate of the array region. A material of the first isolation structures is different from a material of the second isolation structures. A width of each of the first isolation structures is greater than a width of each of the second isolation structures.

Abstract: Provided is a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a periphery region and an array region. The first isolation structures are located in the substrate of the periphery region. The second isolation structures are located in the substrate of the array region. A material of the first isolation structures is different from a material of the second isolation structures. A width of each of the first isolation structures is greater than a width of each of the second isolation structures.

Abstract: A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.

Abstract: A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.

Abstract: A memory device and a method for fabricating the same are provided. A memory device includes a tunneling dielectric layer located on a substrate. The floating gate includes a first doped portion on the tunneling dielectric layer and a second doped portion located on the first doped portion. The first doped portion includes a first dopant and a second dopant, and the second doped portion includes the first dopant. The grain size of the first doped portion is smaller than the grain size of the second doped portion, and the grain size of the first doped portion is between 150 ? to 200 ?. The memory device further includes an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. A source region and a drain region are located in the substrate besides sidewalls of the floating gate.

Abstract: The method for fabricating a semiconductor device is provided. A doped semiconductor layer is formed over the substrate. The doped semiconductor layer is patterned to form a plurality of doped semiconductor patterns. An implantation process is performed to implant a dopant into the doped semiconductor patterns. A process temperature of the implantation process is no more than about ?50° C. The dopants of the implantation process and the doped semiconductor patterns have the same conductivity type.

Abstract: Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device. The method comprises providing a substrate, forming an insulating layer over the substrate, and forming a conductive structure over the insulating layer. The conductive structure is formed by forming a first conductive layer, performing a degassing preparation process over a surface of the first conductive layer to substantially prevent a degassing of the first conductive layer from reaching a second conductive layer, and forming the second conductive layer over the first conductive layer.

Abstract: A method of manufacturing a flash memory is provided. In the method, a hydrogen treatment is performed on a substrate, on which a polysilicon gate and a plurality of spacers on sidewalls of the polysilicon gate are formed. A silicon thin film is deposited on the polysilicon gate to extend a top area thereof. The hydrogen treatment and the deposition of the silicon thin film are accomplished repeatedly, and then a cobalt layer is deposited on the silicon thin film. A portion of the cobalt layer is converted to a CoSix layer, and the unreacted cobalt layer is then removed.

Abstract: The method for fabricating a semiconductor device is provided. A doped semiconductor layer is formed over the substrate. The doped semiconductor layer is patterned to form a plurality of doped semiconductor patterns. An implantation process is performed to implant a dopant into the doped semiconductor patterns. A process temperature of the implantation process is no more than about ?50° C. The dopants of the implantation process and the doped semiconductor patterns have the same conductivity type.

Abstract: A semiconductor device includes polysilicon layer and a metal silicide layer. The polysilicon layer is doped with carbon or phosphorous. The silicide layer is formed over the polysilicon layer.

Abstract: A semiconductor device includes polysilicon layer and a metal silicide layer. The polysilicon layer is doped with carbon or phosphorous. The silicide layer is formed over the polysilicon layer.

Abstract: The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) etching a metal-silicide layer and a POLY layer via a hard mask, wherein the metal-silicide layer is disposed on the POLY layer; (b) forming a POLY recess in the POLY layer; and (c) forming a liner film covering the metal-silicide layer.

Abstract: A semiconductor device includes a substrate, a semiconductor layer, and a material layer. The semiconductor layer is formed over the substrate. The material layer is formed over the semiconductor layer. The semiconductor layer and the material layer have a tapered profile in a vertical direction extending from the substrate.

Abstract: An improved gate structure is provided whereby the gate structure is defined by a trench, the trench having a first oxide layer and a second oxide layer. The invention also provides methods for fabricating the gate structure of the invention defined by a trench having a first oxide layer and a second oxide layer.

Abstract: A method of forming a semiconductor device is provided. The method includes providing a semiconductor substrate, and forming a first conductive layer over the substrate. In one example, an insulating layer may be formed over the semiconductor substrate, with the first conductive layer being formed over the insulating layer. The method also includes forming an interpoly dielectric layer over the first conductive layer. In this regard, forming the interpoly dielectric layer includes forming a silicon oxide layer, and subjecting the silicon oxide layer to oxide densification to form an oxide-densified silicon oxide layer. And the method includes forming a second conductive layer over the interpoly dielectric layer.

Abstract: The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) etching a metal-silicide layer and a POLY layer via a hard mask, wherein the metal-silicide layer is disposed on the POLY layer; (b) forming a POLY recess in the POLY layer; and (c) forming a liner film covering the metal-silicide layer.

Abstract: A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low thermal budget processes.

Abstract: A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low thermal budget processes.