Patents by Inventor Jung-Dal Choi
Jung-Dal Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240081071Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first stack structure including a word line of a first group and select lines of a first group; a second stack structure including select lines of a second group; a first plug in the first stack structure; a second plug connected to the first plug, the second plug being disposed in the second stack structure; a first isolation pattern between the select lines of the first group; and a second isolation pattern between the select lines of the second group.Type: ApplicationFiled: February 27, 2023Publication date: March 7, 2024Applicant: SK hynix Inc.Inventors: Jung Shik JANG, Mi Seong PARK, In Su PARK, Won Geun CHOI, Jung Dal CHOI
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Publication number: 20240049466Abstract: A memory device, and a method of manufacturing the same, includes a stacked structure including gate lines stacked to be spaced apart from each other. The memory device also includes a first channel structure vertical to the gate lines and including a major axis in a first direction. The memory device further includes a second channel structure configured to separate the first channel structure and including a major axis in a second direction orthogonal to the first direction. The first channel structure includes a first memory cell group and a second memory cell group separated from each other by the second channel structure. The second channel structure includes a third memory cell group and a fourth memory cell group separated from each other in the second direction.Type: ApplicationFiled: February 6, 2023Publication date: February 8, 2024Applicant: SK hynix Inc.Inventors: Won Geun CHOI, Mi Seong PARK, In Su PARK, Jung Shik JANG, Jung Dal CHOI
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Publication number: 20230186989Abstract: The present discloses provides a memory device and a method of operating the memory device. The memory device includes first main plugs formed in a vertical direction over a substrate and arranged in a first direction, second main plugs, third main plugs arranged between the first and second main plugs, the third main plugs adjacent to the first and second main plugs, and bit lines above the first to third main plugs, wherein each of the first to third main plugs includes first and second sub-plugs facing each other, wherein portions of the first and second sub-plugs included in each of the first and third main plugs are coupled to different select lines, and wherein portions of the first and second sub-plugs included in each of the second and third main plugs are coupled to different select lines.Type: ApplicationFiled: May 17, 2022Publication date: June 15, 2023Applicant: SK hynix Inc.Inventors: Jung Shik JANG, In Su PARK, Woo Pyo JEONG, Jung Dal CHOI, Jae Woong KIM, Jeong Hwan KIM
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Publication number: 20230093683Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.Type: ApplicationFiled: November 29, 2022Publication date: March 23, 2023Applicant: SK hynix Inc.Inventors: Jung Dal CHOI, Jung Shik JANG, Jin Kook KIM, Dong Sun SHEEN, Se Young OH, Ki Hong LEE, Dong Hun LEE, Sung Hoon LEE, Sung Yong CHUNG
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Publication number: 20230093329Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.Type: ApplicationFiled: November 29, 2022Publication date: March 23, 2023Applicant: SK hynix Inc.Inventors: Jung Dal CHOI, Jung Shik JANG, Jin Kook KIM, Dong Sun SHEEN, Se Young OH, Ki Hong LEE, Dong Hun LEE, Sung Hoon LEE, Sung Yong CHUNG
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Patent number: 11545190Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.Type: GrantFiled: November 13, 2019Date of Patent: January 3, 2023Assignee: SK hynix Inc.Inventors: Jung Dal Choi, Jung Shik Jang, Jin Kook Kim, Dong Sun Sheen, Se Young Oh, Ki Hong Lee, Dong Hun Lee, Sung Hoon Lee, Sung Yong Chung
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Publication number: 20220344366Abstract: A semiconductor device includes a gate structure including conductive layers and insulating layers alternately stacked with each other, channel structures passing through the gate structure and arranged in a first direction, a cutting structure extending in the first direction and passing through the channel structures, and a first slit structure passing through the gate structure and extending in a second direction crossing the first direction.Type: ApplicationFiled: September 23, 2021Publication date: October 27, 2022Applicant: SK hynix Inc.Inventors: Mi Seong PARK, Jang Won KIM, In Su PARK, Jung Shik JANG, Won Geun CHOI, Jung Dal CHOI
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Publication number: 20220319924Abstract: There may be provided a method of manufacturing a semiconductor chip. A layer stack in which first material layers and second material layers are alternately stacked is formed on a semiconductor substrate that includes a chip region and a scribe lane region, and crack propagation guides are formed in a first portion of the layer stack within the scribe lane region.Type: ApplicationFiled: March 29, 2022Publication date: October 6, 2022Applicant: SK hynix Inc.Inventors: In Su PARK, Jung Dal CHOI
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Patent number: 11037953Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.Type: GrantFiled: June 5, 2019Date of Patent: June 15, 2021Assignee: SK hynix Inc.Inventors: Sung Bo Shim, Jung Dal Choi
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Publication number: 20210020203Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.Type: ApplicationFiled: November 13, 2019Publication date: January 21, 2021Applicant: SK hynix Inc.Inventors: Jung Dal CHOI, Jung Shik JANG, Jin Kook KIM, Dong Sun SHEEN, Se Young OH, Ki Hong LEE, Dong Hun LEE, Sung Hoon LEE, Sung Yong CHUNG
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Patent number: 10644026Abstract: A semiconductor device includes: a stack structure; a source connection structure penetrating the stack structure; n first channel rows located at one side of the source connection structure, the n first channel rows including channel patterns; and n+k second channel rows located at the other side of the source connection structure, at least one channel row among the n+k second channel rows including dummy channel patterns, wherein the n and k are integers.Type: GrantFiled: December 21, 2018Date of Patent: May 5, 2020Assignee: SK hynix Inc.Inventors: Nam Jae Lee, Jung Dal Choi
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Publication number: 20190363100Abstract: A semiconductor device includes: a stack structure; a source connection structure penetrating the stack structure; n first channel rows located at one side of the source connection structure, the n first channel rows including channel patterns; and n+k second channel rows located at the other side of the source connection structure, at least one channel row among the n+k second channel rows including dummy channel patterns, wherein the n and k are integers.Type: ApplicationFiled: December 21, 2018Publication date: November 28, 2019Inventors: Nam Jae LEE, Jung Dal CHOI
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Publication number: 20190288003Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.Type: ApplicationFiled: June 5, 2019Publication date: September 19, 2019Inventors: Sung Bo Shim, Jung Dal Choi
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Patent number: 10355013Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.Type: GrantFiled: December 21, 2017Date of Patent: July 16, 2019Assignee: SK hynix Inc.Inventors: Sung Bo Shim, Jung Dal Choi
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Publication number: 20180323207Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.Type: ApplicationFiled: December 21, 2017Publication date: November 8, 2018Inventors: Sung Bo SHIM, Jung Dal CHOI
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Patent number: 9761314Abstract: A non-volatile memory device includes a semiconductor substrate and a tunnel insulating layer and a gate electrode. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than in the blocking insulation layer. A minimum field at a blocking insulation layer can be stronger than at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than through the blocking insulation layer.Type: GrantFiled: December 2, 2013Date of Patent: September 12, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Lee, Jung-Dal Choi
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Patent number: 9564435Abstract: A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.Type: GrantFiled: June 29, 2015Date of Patent: February 7, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-ae Chung, Jung-dal Choi, Toshiro Nakanishi, Yu-bin Kim, Gab-jin Nam, Dong-kyu Lee, Guangfan Jiao
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Publication number: 20160329333Abstract: A semiconductor device includes a substrate, a strain-relaxed buffer layer on the substrate, at least one well in the strain-relaxed buffer layer, a first channel layer on the strain-relaxed buffer layer, and a second channel layer on the well. A lattice constant of material constituting the first well is less than a lattice constant of the material constituting the strain-relaxed buffer layer, but a lattice constant of material constituting the second well is greater than the lattice constant of the material constituting the strain-relaxed buffer layer.Type: ApplicationFiled: July 18, 2016Publication date: November 10, 2016Inventors: DONG-KYU LEE, JAE-HWAN LEE, TAE-YONG KWON, SANG-SU KIM, JUNG-DAL CHOI
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Patent number: 9450049Abstract: A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material.Type: GrantFiled: May 13, 2014Date of Patent: September 20, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Yong Kwon, Sang-Su Kim, Jung-Gil Yang, Jung-Dal Choi
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Patent number: 9450025Abstract: A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line.Type: GrantFiled: June 11, 2015Date of Patent: September 20, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jae Jung, Youn-Seon Kang, Jung-Dal Choi