Abstract: A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

Abstract: There is provided, a semiconductor manufacturing apparatus which reduces loss of a process gas or a precursor transferred from a nozzle to a wafer by improving the injection efficiency of the process gas or the precursor from the nozzle to the substrate. The semiconductor manufacturing apparatus includes a boat on which a substrate is loaded in a first direction, an inner tube which covers the boat, a nozzle which extends in the first direction and through which a process gas to be provided to the substrate moves, a nozzle tube which surrounds the nozzle and comprises a gas injection hole for injecting the process gas toward the substrate, and a nozzle protrusion which is connected to the gas injection hole and extends in a second direction, wherein a shortest distance from an end of the nozzle protrusion to the substrate is greater than 0 mm and less than 9 mm.

Abstract: An ALD apparatus includes a first process chamber configured to supply a first source gas and induce adsorption of a first material film. A second process chamber is configured to supply a second source gas and induce adsorption of a second material film. A third process chamber is configured to supply a third source gas and induce absorption of a third material film. A surface treatment chamber is configured to perform a surface treatment process on each of the first to third material films and remove a reaction by-product. A heat treatment chamber is configured to perform a heat treatment process on the substrate on which the first to third material films are adsorbed in a predetermined order and transform the first to third material films into a single compound thin film.

Abstract: A computing system includes memory configured to store instructions and a nozzle library, and a processor configured to access the memory and to execute the instructions. The instructions cause the computing system to select at least one nozzle unit as a selected at least one nozzle unit based on the nozzle library and to place the selected at least one nozzle unit at corresponding location coordinates, to create multiple volume meshes for the process chamber, and to simulate the flow of the gas through the selected at least one nozzle unit in the process chamber based on the multiple volume meshes in the process chamber. The nozzle library includes information about multiple nozzle units of which each has multiple volume meshes formed therein. The nozzle units have different shapes from each other.

Abstract: A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

Abstract: An apparatus for generating 3D shape data of a showerhead includes: a data processor that generates data sets comprising information indicating values of a first distance between an upper surface of a wafer and a showerhead, information indicating positions on the wafer and information about a fluid flow physical quantity value and determines a function representing a relationship among the various information; an input unit that receives condition data comprising a target fluid flow physical quantity value for each of the positions; and a database that stores information about the function. The data processor obtains information about a second distance, which has the target fluid flow physical quantity value, between the upper surface of the wafer and the showerhead at each of the positions, extracts spatial coordinate information of a lower surface of the showerhead, and generates 3D shape data of the showerhead using the spatial coordinate information.

Abstract: A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

Abstract: A hole is formed to pass through preliminary first mold layers and preliminary second mold layers to form first mold layers and mold layers respectively that are alternately stacked in a vertical direction, perpendicular to a lower structure, on the lower structure. The first mold layers are partially etched along a side surface of the hole to form recess regions and recessed first mold layers. Third mold layers are formed in the recess regions to form interlayer insulation layers so that each of the interlayer insulation layers includes a corresponding third mold layer and a corresponding recessed first mold layer that are positioned at the same level in the vertical direction. A first dielectric layer is formed in the hole to cover the third mold layers and the second mold layers stacked on each other. Information storage patterns are formed on the first dielectric layer.

Abstract: An ALD apparatus includes a first process chamber configured to supply a first source gas and induce adsorption of a first material film. A second process chamber is configured to supply a second source gas and induce adsorption of a second material film. A third process chamber is configured to supply a third source gas and induce absorption of a third material film. A surface treatment chamber is configured to perform a surface treatment process on each of the first to third material films and remove a reaction by-product. A heat treatment chamber is configured to perform a heat treatment process on the substrate on which the first to third material films are adsorbed in a predetermined order and transform the first to third material films into a single compound thin film.

Abstract: A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

Abstract: A hole is formed to pass through preliminary first mold layers and preliminary second mold layers to form first mold layers and mold layers respectively that are alternately stacked in a vertical direction, perpendicular to a lower structure, on the lower structure. The first mold layers are partially etched along a side surface of the hole to form recess regions and recessed first mold layers. Third mold layers are formed in the recess regions to form interlayer insulation layers so that each of the interlayer insulation layers includes a corresponding third mold layer and a corresponding recessed first mold layer that are positioned at the same level in the vertical direction. A first dielectric layer is formed in the hole to cover the third mold layers and the second mold layers stacked on each other. Information storage patterns are formed on the first dielectric layer.

Abstract: An apparatus for generating 3D shape data of a showerhead includes: a data processor that generates data sets comprising information indicating values of a first distance between an upper surface of a wafer and a showerhead, information indicating positions on the wafer and information about a fluid flow physical quantity value and determines a function representing a relationship among the various information; an input unit that receives condition data comprising a target fluid flow physical quantity value for each of the positions; and a database that stores information about the function. The data processor obtains information about a second distance, which has the target fluid flow physical quantity value, between the upper surface of the wafer and the showerhead at each of the positions, extracts spatial coordinate information of a lower surface of the showerhead, and generates 3D shape data of the showerhead using the spatial coordinate information.

Abstract: A computing system includes memory configured to store instructions and a nozzle library, and a processor configured to access the memory and to execute the instructions. The instructions cause the computing system to select at least one nozzle unit as a selected at least one nozzle unit based on the nozzle library and to place the selected at least one nozzle unit at corresponding location coordinates, to create multiple volume meshes for the process chamber, and to simulate the flow of the gas through the selected at least one nozzle unit in the process chamber based on the multiple volume meshes in the process chamber. The nozzle library includes information about multiple nozzle units of which each has multiple volume meshes formed therein. The nozzle units have different shapes from each other.

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

Abstract: In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer.

Abstract: A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is defined between structures including the active pattern, the preliminary tunnel insulation pattern and the preliminary charge storage pattern. A preliminary isolation pattern partially fills the trench. A dielectric layer and a control gate electrode layer are formed on the preliminary charge storage pattern and the preliminary isolation pattern. The control gate electrode layer, the dielectric layer, the preliminary charge storage pattern and the preliminary tunnel insulation pattern are patterned to form gate structures including a tunnel insulation pattern, a charge storage pattern, a dielectric layer pattern and a control gate electrode. The preliminary isolation pattern is isotropically etched to form an isolation pattern and a first air gap. An insulating interlayer is formed between the gate structures to keep the first air gap.

Abstract: There are provided methods for manufacturing a semiconductor device including providing a substrate including a metal layer including an oxidized surface layer in a heat treatment chamber, generating hydrogen radicals within the heat treatment chamber and reducing the oxidized surface layer of the metal layer using the hydrogen radicals.

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.