Patents by Inventor Jung-ho Song

Jung-ho Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960319
    Abstract: A memory device is provided. The memory device comprises an internal clock generator configured to receive an external clock signal from a host and generate an internal clock signal in accordance with a chip enable signal, an internal enable signal generator configured to operate based on the internal clock signal and receive an external enable signal from the host and generate an internal enable signal, and a monitoring signal generator configured to output a monitoring signal that is generated based on at least one of the internal clock signal or the internal enable signal to the host.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: April 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Min Choi, Chan Ho Lee, Jung Hak Song, Ju Chang Lee, Woo Jin Jung
  • Patent number: 11955471
    Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: April 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Do, Dal-Hee Lee, Jin-Young Lim, Tae-Joong Song, Jong-Hoon Jung
  • Publication number: 20240105099
    Abstract: The embodiment relates to a data driving device for driving pixels of a display panel. In the data driving device, two adjacent DACs can have different gate loads for the same gray level value so that the fluctuation of the gate load according to the gray level value is reduced.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 28, 2024
    Applicant: LX SEMICON CO., LTD.
    Inventors: Da Sol WON, Kwang Myung KANG, Yong Min KIM, Dong Keun SONG, Jung Min CHOI, Seon Ho HONG
  • Publication number: 20240009211
    Abstract: Provided are pharmaceutical compositions for preventing or treating lung cancer, including cannabidiol (CBD) and an anti-cancer agent as active ingredients, and uses thereof, and the compositions have been confirmed to exhibit significantly superior lung cancer inhibitory activity when combination treated with CBD and etoposide, one of the anti-cancer agents for lung cancer, and the compositions can be utilized to enhance the therapeutic effect of lung cancer.
    Type: Application
    Filed: July 4, 2023
    Publication date: January 11, 2024
    Applicant: NEOCANNBIO CO., LTD.
    Inventors: Jung Yeob HAM, Jeong Kook KIM, Jung Ho SONG, Kyu Hyuk JEONG
  • Publication number: 20230223578
    Abstract: Proposed are a system and a method for pressurizing an all-solid-state secondary battery at high temperature. More particularly, proposed are a system and a method for pressurizing an all-solid-state secondary battery at high temperature, in which a pre-process of high-temperature pressurization for maximizing a contact interface between a solid electrolyte and an active material and minimizing interfacial resistance is automated in such a manner that the fed secondary battery is automatically packed through a vacuum sealing unit and then pressurized at high temperature, thereby shortening a tact time and thus increasing process efficiency.
    Type: Application
    Filed: January 10, 2023
    Publication date: July 13, 2023
    Inventors: Tae Bong OH, Souk Woo LEE, Oh Chul KWON, Jung Ho SONG, Seung A HAN, Sang Rae KIM, Seung Kyu HAN, Ji Hyeon YUN
  • Patent number: 11646736
    Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, a control logic, a level shifter configured to generate a first internal voltage and a second internal voltage lower than the first internal voltage using a received external voltage on the basis of a control signal from the control logic, and a row decoder configured to provide the first and second internal voltages generated by the level shifter to the memory cell array. The level shifter generates the first internal voltage using the external voltage, generates the second internal voltage using the generated first internal voltage in a power-up mode of the semiconductor device, and generates the second internal voltage using the external voltage in a standby mode of the semiconductor device.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Hee Lee, Ho Joon Kim, Jung-Ho Song
  • Publication number: 20220303440
    Abstract: Provided are a hyperspectral sensor including a window, a first focusing part provided on a rear surface of the window and including a plurality of lenses, a first image sensor provided on a rear surface of the first focusing part and having a front surface parallel to the rear surface of the window, a first mirror spaced apart from the first focusing part and the first image sensor and having a front surface inclined with respect to the rear surface of the window, a first optical element spaced apart from the first mirror, a second optical element spaced apart from the first optical element and having a periodic refractive index distribution therein, a second focusing part spaced apart from the second optical element and including a plurality of lenses, and a second image sensor provided on a rear surface of the second focusing part, a hyperspectral imaging system including the hyperspectral sensor, and a hyperspectral imaging method using the hyperspectral imaging system.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 22, 2022
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Jung-Ho SONG
  • Publication number: 20220182056
    Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, a control logic, a level shifter configured to generate a first internal voltage and a second internal voltage lower than the first internal voltage using a received external voltage on the basis of a control signal from the control logic, and a row decoder configured to provide the first and second internal voltages generated by the level shifter to the memory cell array. The level shifter generates the first internal voltage using the external voltage, generates the second internal voltage using the generated first internal voltage in a power-up mode of the semiconductor device, and generates the second internal voltage using the external voltage in a standby mode of the semiconductor device.
    Type: Application
    Filed: July 9, 2021
    Publication date: June 9, 2022
    Inventors: Nam Hee LEE, Ho Joon KIM, Jung-Ho SONG
  • Patent number: 11313723
    Abstract: Provided is a hyperspectral sensor including a spectral angle converting unit configured to convert an angle of incident light differently according to a wavelength, a diffraction unit configured to selectively diffract the incident light according to an incident angle and a wavelength, a focusing optics including at least one lens, and configured to collect diffracted light passing through the diffraction unit, and an image sensor configured to acquire an image passing through the focusing optics and formed on a focal plane, wherein the diffraction unit includes a volume Bragg grating having a periodic refractive index distribution therein.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: April 26, 2022
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Jung-Ho Song
  • Publication number: 20210278275
    Abstract: Provided is a hyperspectral sensor including a spectral angle converting unit configured to convert an angle of incident light differently according to a wavelength, a diffraction unit configured to selectively diffract the incident light according to an incident angle and a wavelength, a focusing optics including at least one lens, and configured to collect diffracted light passing through the diffraction unit, and an image sensor configured to acquire an image passing through the focusing optics and formed on a focal plane, wherein the diffraction unit includes a volume Bragg grating having a periodic refractive index distribution therein.
    Type: Application
    Filed: October 16, 2020
    Publication date: September 9, 2021
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: JUNG-HO SONG
  • Patent number: 10992626
    Abstract: An instant messaging service providing method and a user terminal for performing the instant messaging service providing method including receiving and displaying a first message that is created by a message transmitter; determining whether a message switching condition is met after the first message is displayed; and displaying a second message that is created by the message transmitter when the message switching condition is determined to be met.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: April 27, 2021
    Assignee: KAKAO CORP.
    Inventors: So Young Choi, Bo Mi Kim, Un Bong Kang, Jung Ho Song, Ji Na Kim, Jun Hyuk Jang, Ji Won Suh
  • Patent number: 10878919
    Abstract: A method for initializing a channel in a non-volatile memory device comprising a memory block including a plurality of word lines and a plurality of string selection lines, includes applying a voltage to the plurality of string selection lines; converting a bit line passing through the block into a floating state; and a releasing the floating state of the bit line.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Ho Cho, Kyo Man Kang, Dae Seok Byeon, Jung Ho Song, Chi Weon Yoon
  • Publication number: 20200152275
    Abstract: A method for initializing a channel in a non-volatile memory device comprising a memory block including a plurality of word lines and a plurality of string selection lines, includes applying a voltage to the plurality of string selection lines; converting a bit line passing through the block into a floating state; and a releasing the floating state of the bit line.
    Type: Application
    Filed: May 23, 2019
    Publication date: May 14, 2020
    Inventors: DOO HO CHO, KYO MAN KANG, DAE SEOK BYEON, JUNG HO SONG, CHI WEON YOON
  • Patent number: 10649139
    Abstract: An optical waveguide structure includes a substrate and a core structure disposed on the substrate. The substrate includes a first waveguide region, a second waveguide region, and a transition region between the first waveguide region and the second waveguide region. The core structure includes first core segments arranged in a first direction and a second direction crossing the first direction on the transition region. The core structure includes second core segments arranged in the first direction and the second direction on the second waveguide region. The first direction and the second direction are parallel to a top surface of the substrate.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 12, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Duk Jun Kim, Young-Ho Ko, Dong-Young Kim, Jong-Hoi Kim, Yongsoon Baek, Jung-Ho Song, Dong Hyo Lee, Byung-Seok Choi, Won Seok Han
  • Patent number: 10600488
    Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Song, Se-heon Baek, Yong-sung Cho
  • Publication number: 20190219760
    Abstract: An optical waveguide structure includes a substrate and a core structure disposed on the substrate. The substrate includes a first waveguide region, a second waveguide region, and a transition region between the first waveguide region and the second waveguide region. The core structure includes first core segments arranged in a first direction and a second direction crossing the first direction on the transition region. The core structure includes second core segments arranged in the first direction and the second direction on the second waveguide region. The first direction and the second direction are parallel to a top surface of the substrate.
    Type: Application
    Filed: December 10, 2018
    Publication date: July 18, 2019
    Inventors: Duk Jun KIM, Young-Ho KO, Dong-Young KIM, Jong-Hoi KIM, Yongsoon BAEK, Jung-Ho SONG, Dong Hyo LEE, Byung-Seok CHOI, Won Seok HAN
  • Patent number: 10324629
    Abstract: A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hoon Lee, Eun-Suk Cho, Woo-Pyo Jeong, Sang-Wan Nam, Jung-Ho Song, Yun-Ho Hong, Jae-Hoon Lee
  • Publication number: 20190080770
    Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.
    Type: Application
    Filed: November 12, 2018
    Publication date: March 14, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho SONG, Se-heon BAEK, Yong-sung CHO
  • Patent number: 10192624
    Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Song, Se-heon Baek, Yong-sung Cho
  • Publication number: 20180292989
    Abstract: A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.
    Type: Application
    Filed: January 12, 2018
    Publication date: October 11, 2018
    Inventors: JONG-HOON LEE, EUN-SUK CHO, WOO-PYO JEONG, SANG-WAN NAM, JUNG-HO SONG, YUN-HO HONG, JAE-HOON LEE