Abstract: A battery pack includes a battery module having at least one battery cell, a pack case configured to accommodate the battery module, and a connection guide unit provided on at least one side of the pack case and configured to be accessible to electrical members of two or more connection types.

Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.

Abstract: An operation method of a relay node may include: receiving, from a first communication node, first data composed of n bits; receiving, from a second communication node, second data composed of m bits; in response to determining that n is greater than m, generating first T-data of m bits excluding (n-m) bits from the n-bits of the first data and first R-data of (n-m) bits; generating third data by performing a network coding operation on the first T-data and the second data; transmitting the third data to the first communication node; and transmitting the third data and the first R-data to the second communication node.

Abstract: A method for configuring multi-vision by an electronic device is provided. The method includes obtaining, by the electronic device, a user input, generating first user input information from the obtained user input, determining whether the electronic device is one of a master device and a slave device, when the electronic device is determined to be the master device, obtaining second user input information from one or more other electronic devices, and determining an arrangement structure of one of the master device and the slave device based on one of the first user input information and the second user input information.

Abstract: Provided are methods for changing a display range in an electronic device having a touchscreen. The method for changing a display range in an electronic device includes: detecting a plurality of touches; determining a plurality of regions in consideration of a plurality of touch points; and changing a display range of at least one region of the plurality of regions in consideration of change in a distance between the plurality of touch points.

Abstract: Provided are methods for changing a display range in an electronic device having a touchscreen. The method for changing a display range in an electronic device includes: detecting a plurality of touches; determining a plurality of regions in consideration of a plurality of touch points; and changing a display range of at least one region of the plurality of regions in consideration of change in a distance between the plurality of touch points.

Abstract: Provided are methods for changing a display range in an electronic device having a touchscreen. The method for changing a display range in an electronic device includes: detecting a plurality of touches; determining a plurality of regions in consideration of a plurality of touch points; and changing a display range of at least one region of the plurality of regions in consideration of change in a distance between the plurality of touch points.

Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.

Abstract: A method for configuring multi-vision by an electronic device is provided. The method includes obtaining, by the electronic device, a user input, generating first user input information from the obtained user input, determining whether the electronic device is one of a master device and a slave device, when the electronic device is determined to be the master device, obtaining second user input information from one or more other electronic devices, and determining an arrangement structure of one of the master device and the slave device based on one of the first user input information and the second user input information.

Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.

Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.

Abstract: Provided are methods for changing a display range in an electronic device having a touchscreen. The method for changing a display range in an electronic device includes: detecting a plurality of touches; determining a plurality of regions in consideration of a plurality of touch points; and changing a display range of at least one region of the plurality of regions in consideration of change in a distance between the plurality of touch points.

Abstract: A method for forming a metal line in a flash memory device includes sequentially forming a first inter-layer insulation layer, an etch stop layer, a second inter-layer insulation layer, and a hard mask layer over a substrate where a contact plug is formed, etching the hard mask layer to form a hard mask pattern, performing a first etching process on the second inter-layer insulation layer to form a trench exposing a portion of the etch stop layer, performing a second etching process to selectively remove the hard mask pattern and the exposed portion of the etch stop layer, forming a spacer over sidewalls of the trench, and forming a metal line filling the trench to make contact with the contact plug. The hard mask layer and the etch stop layer include substantially the same material. The spacer includes substantially the same material as the first and second inter-layer insulation layers.

Abstract: A method for forming a metal line in a flash memory device includes sequentially forming a first inter-layer insulation layer, an etch stop layer, a second inter-layer insulation layer, and a hard mask layer over a substrate where a contact plug is formed, etching the hard mask layer to form a hard mask pattern, performing a first etching process on the second inter-layer insulation layer to form a trench exposing a portion of the etch stop layer, performing a second etching process to selectively remove the hard mask pattern and the exposed portion of the etch stop layer, forming a spacer over sidewalls of the trench, and forming a metal line filling the trench to make contact with the contact plug. The hard mask layer and the etch stop layer include substantially the same material. The spacer includes substantially the same material as the first and second inter-layer insulation layers.

Abstract: The present invention is provided to manufacture a dual gate oxide film. According to the present invention, it is possible to obtain a high-quality NO gate oxide film for high voltage and a high-quality NO gate oxide film for low voltage where nitrogen is distributed uniformly in the entire oxide films by carrying out a rapid annealing process in an inert atmosphere after carrying out an NO annealing process in order to prevent a phenomenon that nitrogen is not distributed uniformly and segregated in a gate oxide film for high voltage due to application of the NO annealing process after forming a gate oxide film for low voltage.

Abstract: The present invention is provided to manufacture a dual gate oxide film. According to the present invention, it is possible to obtain a high-quality NO gate oxide film for high voltage and a high-quality NO gate oxide film for low voltage where nitrogen is distributed uniformly in the entire oxide films by carrying out a rapid annealing process in an inert atmosphere after carrying out an NO annealing process in order to prevent a phenomenon that nitrogen is not distributed uniformly and segregated in a gate oxide film for high voltage due to application of the NO annealing process after forming a gate oxide film for low voltage.

Abstract: Disclosed is a method of forming a floating gate in a date flash memory device on which first and second polysilicon films are stacked. After the first polysilicon film is formed, a SiH4 gas is introduced to decompose SiH4 and SiO2 into Si and H2 and Si and O2. A N2 anneal process is then implemented so that the decomposed H2 gas and O2 gas react to a N2 gas and are then outgassed. Next, a SiH4 gas and a PH3 gas are introduced to form the second polysilicon film. A native oxide film within the interface of the first polysilicon film and the second polysilicon film is removed to improve characteristics of the data flash memory device.

Abstract: Disclosed is a method of forming a floating gate in a date flash memory device on which first and second polysilicon films are stacked. After the first polysilicon film is formed, a SiH4 gas is introduced to decompose SiH4 and SiO2 into Si and H2 and Si and O2. A N2 anneal process is then implemented so that the decomposed H2 gas and O2 gas react to a N2 gas and are then outgassed. Next, a SiH4 gas and a PH3 gas are introduced to form the second polysilicon film. A native oxide film within the interface of the first polysilicon film and the second polysilicon film is removed to improve characteristics of the data flash memory device.

Abstract: A method of manufacturing a flash memory cell is disclosed. The method comprises the steps of forming an oxide film on a semiconductor substrate in which a device separation film is formed and then patterning the oxide film to expose the semiconductor substrate at a portion in which a floating gate will be formed; sequentially forming a tunnel oxide film and a first polysilicon layer on the entire structure, and then flattening the first polysilicon layer until the tunnel oxide film is exposed to form a floating gate; etching the tunnel oxide film and the oxide film in the exposed portion to a given thickness and the forming a dielectric film on the entire structure; sequentially forming a second polysilicon layer, a tungsten silicide layer and a hard mask and then patterning them to form a control gate; and injecting impurity ions into the semiconductor substrate at the both sides of the floating gate to form a junction region.