Patents by Inventor Jung-June Park
Jung-June Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128935Abstract: A differential signaling circuit is provided. The differential signaling circuit includes: a differential amplifier configured to generate differential signals; a first signal path circuit; a second signal path circuit; a phase control circuit configured to receive the differential signals having a common phase, output DC signals having a common level in a first operating period, and transmit the differential signals to the first signal path circuit and the second signal path circuit, respectively, in a second operating period; and a duty ratio correction circuit connected between the first signal path circuit and the second signal path circuit, and configured to control duty ratios of the differential signals to be equal to each other in the second operating period.Type: ApplicationFiled: July 12, 2023Publication date: April 18, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jehoon KIM, DONGHO SHIN, JUNG-JUNE PARK, HYUNSUK KANG, CHIWEON YOON
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Patent number: 11948547Abstract: An active noise control system selects one reference sensor providing a reference signal with the largest coherence to a noise signal, among a plurality of available reference sensors, as a first entry of a reference sensor set. After selecting the first entry, the active noise control system repeats a process in which a sensor capable of providing the largest information quantity to a current reference sensor set among remaining sensors is selected as a new entry of a reference sensor set, until a desired number of sensors is reached or a desired control level is reached. When the reference sensor set is determined, the active noise control system utilizes the entries of the reference sensor set to generates a noise control signal suitable for canceling the noise signal.Type: GrantFiled: September 2, 2022Date of Patent: April 2, 2024Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION, SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Mun Hwan Cho, Kaang Dok Yee, Chi Sung Oh, Jung Keun You, Yun Seol Park, Yeon June Kang
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Patent number: 11923564Abstract: A method for producing a battery module is provided. The method for producing a battery module includes: stacking a plurality of battery cells; disposing a plurality of bus bars adjacent to electrode leads respectively provided at the plurality of battery cells; by a welding jig, pressing the electrode leads so that the electrode leads come into contact with the bus bars, respectively; and welding the electrode leads and the bus bars through an opening formed in the welding jig.Type: GrantFiled: May 10, 2022Date of Patent: March 5, 2024Assignee: LG ENERGY SOLUTION, LTD.Inventors: Ho-June Chi, Jung-Hoon Lee, Jeong-O Mun, Jin-Yong Park
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Patent number: 11917898Abstract: A display device includes: a substrate including a display area and a folding area positioned in a portion of the display area; a display structure disposed on the substrate; a protection film disposed on the substrate and overlapping the folding area; an adhesive member disposed between the protection film and the substrate, wherein the protection film adheres to the substrate by the adhesive member; a first antistatic layer disposed between the protection film and the adhesive member, wherein the first antistatic layer includes a first compound; a second antistatic layer disposed on a bottom surface of the protection film, wherein the second antistatic layer includes a second compound; and a supporting member disposed on the second antistatic layer, wherein the supporting member includes an opening overlapping the folding area.Type: GrantFiled: October 31, 2022Date of Patent: February 27, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Sung June Park, Jung-Hun Lee, Ji Hwa Lee
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Publication number: 20240021259Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: ApplicationFiled: July 28, 2023Publication date: January 18, 2024Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Patent number: 11804270Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.Type: GrantFiled: August 30, 2021Date of Patent: October 31, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Yeon Shin, Jeong-Don Ihm, Byung-Hoon Jeong, Jung-June Park
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Publication number: 20230335203Abstract: A storage system includes a memory controller providing a clock signal; a buffer having a first duty cycle corrector to receive the clock signal and a chip selection signal from the memory controller, perform a first duty correction operation on the clock signal using a first data code and output a first corrected clock signal, a register to store the first data code regarding the chip selection signal, and a sampler to receive a data signal and a data strobe signal regarding the data signal and output a data stream; and a nonvolatile memory having a second duty cycle corrector to receive the first corrected clock signal from the buffer and perform a second duty correction operation on the first corrected clock signal using a second data code and out a second corrected clock signal, a second data code generation circuit to generate the second data code based on the second corrected clock signal, and a data strobe signal generator to generate the data strobe signal based on the second corrected clock signal anType: ApplicationFiled: June 22, 2023Publication date: October 19, 2023Inventors: TongSung KIM, Dae Hoon NA, Jung-June PARK, Dong Ho SHIN, Byung Hoon JEONG, Young Min JO
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Publication number: 20230298639Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Patent number: 11742040Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: GrantFiled: March 25, 2022Date of Patent: August 29, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Publication number: 20230240076Abstract: Disclosed are semiconductor devices and semiconductor packages. The semiconductor device comprises a semiconductor substrate that includes a stack region and a pad region, a peripheral circuit structure that includes a plurality of peripheral circuits on the semiconductor substrate, a cell array structure on the peripheral circuit structure, and a redistribution layer on the cell array structure and including a redistribution dielectric layer and a redistribution pattern on the redistribution dielectric layer. The redistribution dielectric layer covers an uppermost conductive pattern of the cell array structure. The redistribution pattern is connected to the uppermost conductive pattern. A thickness in a vertical direction of the redistribution layer on the pad region is greater than that of the redistribution layer on the stack region.Type: ApplicationFiled: November 11, 2022Publication date: July 27, 2023Inventors: SANG-LOK KIM, SANG SOO PARK, JUNG-JUNE PARK, SU CHANG JEON, SUNG-MIN JOE
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Patent number: 11705166Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.Type: GrantFiled: February 23, 2021Date of Patent: July 18, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Patent number: 11699492Abstract: A storage system includes: a memory controller which provides a clock signal; a buffer which receives the clock signal and re-drives the clock signal, the buffer including a sampler which receives a data signal and a data strobe signal regarding the data signal, and which outputs a data stream; and a nonvolatile memory, including: a first duty cycle corrector, which receives the clock signal outputs a corrected clock signal by performing a first duty correction operation on the clock signal; and a data strobe signal generator, which generates the data strobe signal based on the corrected clock signal and provides the data strobe signal to the buffer. The buffer receives the data strobe signal output from the nonvolatile memory, senses a duty ratio of the data strobe signal input to the sampler, and performs a second duty correction operation on the duty ratio of the input data strobe signal.Type: GrantFiled: July 19, 2021Date of Patent: July 11, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: TongSung Kim, Dae Hoon Na, Jung-June Park, Dong Ho Shin, Byung Hoon Jeong, Young Min Jo
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Publication number: 20220215892Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: ApplicationFiled: March 25, 2022Publication date: July 7, 2022Inventors: Eun-ji KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Patent number: 11342038Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: GrantFiled: January 29, 2021Date of Patent: May 24, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Publication number: 20220122675Abstract: A storage system includes: a memory controller which provides a clock signal; a buffer which receives the clock signal and re-drives the clock signal, the buffer including a sampler which receives a data signal and a data strobe signal regarding the data signal, and which outputs a data stream; and a nonvolatile memory, including: a first duty cycle corrector, which receives the clock signal outputs a corrected clock signal by performing a first duty correction operation on the clock signal; and a data strobe signal generator, which generates the data strobe signal based on the corrected clock signal and provides the data strobe signal to the buffer. The buffer receives the data strobe signal output from the nonvolatile memory, senses a duty ratio of the data strobe signal input to the sampler, and performs a second duty correction operation on the duty ratio of the input data strobe signal.Type: ApplicationFiled: July 19, 2021Publication date: April 21, 2022Inventors: TongSung KIM, Dae Hoon NA, Jung-June PARK, Dong Ho SHIN, Byung Hoon JEONG, Young Min JO
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Patent number: 11257531Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.Type: GrantFiled: January 27, 2021Date of Patent: February 22, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
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Publication number: 20210391023Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Inventors: Ji-yeon SHIN, Jeong-don IHM, Byung-hoon JEONG, Jung-june PARK
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Patent number: 11114171Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.Type: GrantFiled: September 2, 2020Date of Patent: September 7, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-yeon Shin, Jeong-don Ihm, Byung-hoon Jeong, Jung-june Park
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Publication number: 20210201964Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.Type: ApplicationFiled: February 23, 2021Publication date: July 1, 2021Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Patent number: 11024400Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: GrantFiled: April 30, 2020Date of Patent: June 1, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi