Abstract: A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.

Abstract: Ultrasound devices are disclosed. The ultrasound devices have an elevational dimension. Different percentages of the aperture of the ultrasound device corresponding to different percentages of the elevational dimension are utilized in different applications. The resolution of imagine may be adjusted in connection with usage of different percentages of the aperture.

Abstract: Aspects of the technology described herein relate to control circuitry configured to turn on and off the ADC driver. In some embodiments, the control circuitry is configured to turn on and off the ADC driver in synchronization with sampling activity of an ADC, in particular based on when an ADC is sampling. The control circuitry may be configured to turn on the ADC driver during the hold phase of the ADC a time period before the track phase and to turn off the ADC driver during the hold phase a time period after the track phase. In some embodiments, the control circuitry is configured to control a duty cycle of the ADC driver turning on and off. In some embodiments, the control circuitry is configured to control a ratio between an off current and an on current in the ADC driver.

Abstract: A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.

Abstract: Aspects of the technology described herein related to an ultrasound processing unit (UPU) including gray-coding circuitry configured to convert standard binary-coded digital ultrasound signals to gray-coded digital ultrasound signals and gray-decoding circuitry coupled to the gray-coding circuitry and configured to convert the gray-coded digital ultrasound signals to standard binary-coded digital ultrasound signals. The UPU may include an analog portion, a digital portion, and a data bus configured to route the gray-coded digital ultrasound signals from the analog portion to the digital portion subsequent to converting the standard binary-coded digital ultrasound signals to the gray-coded digital ultrasound signals. The analog portion may include multiple analog front-ends (AFEs), the gray-coding circuitry, and an analog-to-digital converter. The digital portion may include the gray-decoding circuitry. A data bus from one AFE may pass over another AFE.

Abstract: Aspects of the technology described herein relate to control circuitry configured to turn on and off the ADC driver. In some embodiments, the control circuitry is configured to turn on and off the ADC driver in synchronization with sampling activity of an ADC, in particular based on when an ADC is sampling. The control circuitry may be configured to turn on the ADC driver during the hold phase of the ADC a time period before the track phase and to turn off the ADC driver during the hold phase a time period after the track phase. In some embodiments, the control circuitry is configured to control a duty cycle of the ADC driver turning on and off. In some embodiments, the control circuitry is configured to control a ratio between an off current and an on current in the ADC driver.

Abstract: Aspects of the technology described herein related to an ultrasound processing unit (UPU) including gray-coding circuitry configured to convert standard binary-coded digital ultrasound signals to gray-coded digital ultrasound signals and gray-decoding circuitry coupled to the gray-coding circuitry and configured to convert the gray-coded digital ultrasound signals to standard binary-coded digital ultrasound signals. The UPU may include an analog portion, a digital portion, and a data bus configured to route the gray-coded digital ultrasound signals from the analog portion to the digital portion subsequent to converting the standard binary-coded digital ultrasound signals to the gray-coded digital ultrasound signals. The analog portion may include multiple analog front-ends (AFEs), the gray-coding circuitry, and an analog-to-digital converter. The digital portion may include the gray-decoding circuitry. A data bus from one AFE may pass over another AFE.

Abstract: Aspects of the technology described herein relate to a pipeline configured to pipeline ultrasound signals from multiple analog front-ends (AFEs) to a digital portion of an ultrasound processing unit. The ultrasound signals may be digital ultrasound signals from analog-to-digital converters of the multiple AFEs. The pipeline may include first pipelining circuitry in a first AFE and second pipelining circuitry in a second AFE. The first pipelining circuitry may be configured to output a first digital ultrasound signal from the first pipelining circuitry to the digital portion of the UPU, receive a second digital ultrasound signal from second pipelining circuitry, and output the second digital ultrasound signal from the first pipelining circuitry to the digital portion of the UPU. De-interleaving circuitry may be coupled to the first pipelining circuitry and configured to de-interleave the first digital ultrasound signal and the second digital ultrasound signal outputted by the first pipelining circuitry.

Abstract: A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.

Abstract: A sensor device includes a sensor array and a flow cell in fluid communication with the sensor array. Bias circuitry apply bias arrangements to the sensor array to produce sensor data. Peripheral circuitry coupled to the bias circuitry produces streams of data from the sensor array, the peripheral circuitry having an active mode and an idle mode. Logic to switch the peripheral circuitry between the active mode and the idle mode to control power consumption is provided. A temperature sensor may be included, and the logic can operate with feedback to switch between the active mode and the idle mode to maintain the temperature within an operating range.

Abstract: A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.

Abstract: An ultrasound device is described. The ultrasound device may include a cavity, a membrane, and a sensing electrode. When an electrical signal is applied to the sensing electrode and a static bias is applied to the membrane, the membrane vibrates within the cavity and produces ultrasonic signals. The cavity, the membrane, and the sensing electrode may be considered a capacitive micromachined ultrasonic transducer (CMUT). The sensing electrode may be shaped as a ring, whereby the central portion of the sensing electrode is removed. Removal of the central portion of the sensing electrode may reduce the parasitic capacitance without substantially affecting the production of ultrasonic signals by the CMUT. This, in turn, can result in an increase in the signal-to-noise ratio (SNR) of the ultrasonic signals. The ultrasound device may further include a bond pad configured for wire bonding, and a trench electrically isolating the bond pad from the membrane.

Abstract: Micromachined ultrasonic transducers having pressure ports are described. The micromachined ultrasonic transducers may comprise flexible membranes configured to vibrate over a cavity. The cavity may be sealed, in some instances by the membrane itself. A pressure port may provide access to the cavity, and thus control of the cavity pressure. In some embodiments, an ultrasound device including an array of micromachined ultrasonic transducers is provided, with pressure ports for at least some of the ultrasonic transducers. The pressure ports may be used to control pressure across the array.

Abstract: A sensor device includes a sensor array and a flow cell in fluid communication with the sensor array. Bias circuitry apply bias arrangements to the sensor array to produce sensor data. Peripheral circuitry coupled to the bias circuitry produces streams of data from the sensor array, the peripheral circuitry having an active mode and an idle mode. Logic to switch the peripheral circuitry between the active mode and the idle mode to control power consumption is provided. A temperature sensor may be included, and the logic can operate with feedback to switch between the active mode and the idle mode to maintain the temperature within an operating range.

Abstract: A sensor device includes a sensor array and a flow cell in fluid communication with the sensor array. Bias circuitry apply bias arrangements to the sensor array to produce sensor data. Peripheral circuitry coupled to the bias circuitry produces streams of data from the sensor array, the peripheral circuitry having an active mode and an idle mode. Logic to switch the peripheral circuitry between the active mode and the idle mode to control power consumption is provided. A temperature sensor may be included, and the logic can operate with feedback to switch between the active mode and the idle mode to maintain the temperature within an operating range.

Abstract: A sensor device includes a sensor array and a flow cell in fluid communication with the sensor array. Bias circuitry apply bias arrangements to the sensor array to produce sensor data. Peripheral circuitry coupled to the bias circuitry produces streams of data from the sensor array, the peripheral circuitry having an active mode and an idle mode. Logic to switch the peripheral circuitry between the active mode and the idle mode to control power consumption is provided. A temperature sensor may be included, and the logic can operate with feedback to switch between the active mode and the idle mode to maintain the temperature within an operating range.

Abstract: A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.

Abstract: An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.

Abstract: An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.

Abstract: An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.