Abstract: A semiconductor imager structure having a photodiode being provided as a well region formed within a substrate layer and a transistor electrically connected to the photodiode and having a terminal that has a same electrical potential as the photodiode. The well region of the photodiode having an extended portion so that at least a portion of the terminal of the transistor has the same electrical potential as the photodiode is formed within the extended portion of the well region of the photodiode.

Abstract: An image capture system for mobile communications systems includes an imaging device for capturing optical image data and a data transfer apparatus coupled to a communications device communications device for transferring the optical image data to the communications device for transmittal over a communications network.

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

Abstract: A single stack bipolar logic AND gate for low power applications comprising: a first differential pair of transistors, each transistor of the first differential pair having base, emitter and collector terminals, a base of a first transistor of the first differential pair receiving an input signal A and a base of the second transistor of the first differential pair receiving its complement signal {overscore (A)}, the emitters of each transistor of the first differential pair being connected at a common node to a first constant current source; a second differential pair of transistors, each transistor of the second differential pair having base, emitter and collector terminals, a base of a first transistor of the second differential pair receiving an input signal B and a base of the second transistor of the second differential pair receiving its complement signal {overscore (B)}, the emitters of each transistor of the second differential pair being connected at a common node to a second constant current source;

Abstract: A system and method of controlling the operation of linear variable-gain amplifiers to allow for such linear variable gain amplifiers to have a wider operating range at high current levels, control inputs for selectable gains and improved low-voltage operation. In a first mode, the amplifier includes an additional source of current to allow for an enhanced operating range. In a second embodiment, the amplifier includes a plurality of selective resistive levels and a selection system which allows the selection of one of the resistive levels which, in turn, controls the gain range of the amplifier system of the present invention. A third embodiment of the present invention illustrates the use of an amplifier system useful for a low voltage input signal to reduce errors caused by variations in the base to emitter in the two transistors providing the amplification.

Abstract: A system and method of controlling the operation of linear variable-gain amplifiers to allow for such linear variable gain amplifiers to have a wider operating range at high current levels, control inputs for selectable gains and improved low-voltage operation. In a first mode, the amplifier includes an additional source of current to allow for an enhanced operating range. In a second embodiment, the amplifier includes a plurality of selective resistive levels and a selection system which allows the selection of one of the resistive levels which, in turn, controls the gain range of the amplifier system of the present invention. A third embodiment of the present invention illustrates the use of an amplifier system useful for a low voltage input signal to reduce errors caused by variations in the base to emitter in the two transistors providing the amplification.

Abstract: An analog-to-digital converter (ADC), including a plurality of first-level folded-differential-logic-encoders (FDLEs), coupled to receive an analog input signal and respective reference voltages and to provide respective outputs responsive to comparing a magnitude of the input signal to the respective reference voltages. The ADC has a second-level resultant FDLE, which is coupled to receive and combine the outputs of the first-level FDLEs to provide a digital value indicative of the magnitude of the input signal.

Abstract: A system and method of controlling the operation of linear variable-gain amplifiers to allow for such linear variable gain amplifiers to have a wider operating range at high current levels, control inputs for selectable gains and improved low-voltage operation. In a first mode, the amplifier includes an additional source of current to allow for an enhanced operating range. In a second embodiment, the amplifier includes a plurality of selective resistive levels and a selection system which allows the selection of one of the resistive levels which, in turn, controls the gain range of the amplifier system of the present invention. A third embodiment of the present invention illustrates the use of an amplifier system useful for a low voltage input signal to reduce errors caused by variations in the base to emitter in the two transistors providing the amplification.

Abstract: In a current mode logic (CML) circuit, a high impedance state is implemented at the output for a bi-directional buffer. The output common mode voltage can be adjusted at the same time, which is particularly useful for a CML off-chip driver.

Abstract: A reference generator having a temperature-dependent output variation that is greater than an absolute temperature variation includes a first source and a second source, the first source generating a proportional to absolute temperature (PTAT) output. The second source generates an output having a temperature coefficient less than or equal to zero. The reference generator further includes a subtraction circuit coupled to the first and second sources, the subtraction circuit operatively subtracting the output of the second source from the PTAT output and generating an offset output, the offset output having a variation greater than an absolute temperature variation. Using the reference generator described herein in accordance with the invention, circuits having a relatively high temperature dependency can be easily compensated. Moreover, the reference generator is suitable for temperature sensing with large temperature dependency without requiring a high supply voltage.

Abstract: In a current mode logic (CML) circuit, a high impedance state is implemented at the output for a bi-directional buffer. The output common mode voltage can be adjusted at the same time, which is particularly useful for a CML off-chip driver.

Abstract: A reference generator having a temperature-dependent output variation that is greater than an absolute temperature variation includes a first source and a second source, the first source generating a proportional to absolute temperature (PTAT) output. The second source generates an output having a temperature coefficient less than or equal to zero. The reference generator further includes a subtraction circuit coupled to the first and second sources, the subtraction circuit operatively subtracting the output of the second source from the PTAT output and generating an offset output, the offset output having a variation greater than an absolute temperature variation. Using the reference generator described herein in accordance with the invention, circuits having a relatively high temperature dependency can be easily compensated. Moreover, the reference generator is suitable for temperature sensing with large temperature dependency without requiring a high supply voltage.

Abstract: A driver circuit having a minimized and/or controllable output common mode voltage comprises a differential amplifier having, a passive element as a biasing source for establishing a bias current in the differential amplifier and a control amplifier operatively coupled to the differential amplifier in a feedback arrangement, the control amplifier generating a control signal. The differential amplifier is responsive to the control signal for providing a voltage at an output of the driver circuit that is substantially independent of an input signal presented to an input of the driver circuit. By eliminating the need for an active device (e.g., transistor) as a bias current source, the output common mode voltage of the driver circuit is minimized. A reference signal coupled to the control amplifier, in conjunction with the feedback arrangement, substantially fixes the output common mode voltage of the driver circuit to a predetermined value.

Abstract: A circuit provides differential logic signals and includes a differential-input circuit having a first differential input and a second differential input. A first unit receives an input voltage signal and a supply voltage for providing a first voltage to the first differential input via a first node. A second unit receives the supply voltage for providing a second voltage to the second differential input via a second node. The differential-input circuit outputs a signal in accordance with the first and second voltages.

Abstract: A circuit provides differential logic signals and includes a differential-input circuit having a first differential input and a second differential input. A first unit receives an input voltage signal and a supply voltage for providing a first voltage to the first differential input via a first node. A second unit receives the supply voltage for providing a second voltage to the second differential input via a second node. The differential-input circuit outputs a signal in accordance with the first and second voltages.

Abstract: A single stack bipolar logic AND gate for low power applications comprising: a first differential pair of transistors, each transistor of the first differential pair having base, emitter and collector terminals, a base of a first transistor of the first differential pair receiving an input signal A and a base of the second transistor of the first differential pair receiving its complement signal {overscore (A)}, the emitters of each transistor of the first differential pair being connected at a common node to a first constant current source; a second differential pair of transistors, each transistor of the second differential pair having base, emitter and collector terminals, a base of a first transistor of the second differential pair receiving an input signal B and a base of the second transistor of the second differential pair receiving its complement signal {overscore (B)}, the emitters of each transistor of the second differential pair being connected at a common node to a second constant current source;

Abstract: An encoding circuit for use with a comparator, includes a plurality of logic elements for receiving an input from a comparator, and a Gray code encoder for receiving an output from the plurality of logic elements. Both first and second type comparator errors (e.g., meta-stability errors and bubble-errors) are substantially eliminated simultaneously by the logic elements.

Abstract: Disclosed is an image sensor including one or more dummy pixels that produce a reference signal which is used to compensate for errors within the devices of the main pixel cells. In one embodiment, at least one dummy pixel is used in conjunction with other circuitry to correct for nonlinearities in the transfer characteristic of a source follower transistor within each pixel. In another embodiment, an array of dummy pixels is used to correct for leakage current within the pixels during an electronic shutter mode of operation. The two techniques can be combined whereby both threshold voltage mismatch and leakage current are compensated for.