Abstract: A deposition mask includes a silicon substrate including cell areas and a mask frame area excluding the cell areas, the mask frame area including a mask rip area partitioning the cell areas and an outer frame area disposed at an outermost portion of the silicon substrate, a mask rip disposed in the mask rip area, a mask membrane disposed in each of the cell areas, a first metal frame disposed in the outer frame area, and a second metal frame surrounding an outer portion of the silicon substrate and connected to the first metal frame.

Abstract: A method of fabricating a mask includes defining cell areas and a mask frame area on a silicon substrate, the mask frame area excluding the cell areas, the mask frame area may include a mask rib region partitioning the cell areas and an outer frame region disposed at an outermost position of the silicon substrate, forming a groove in the mask rib region, forming a metal mask rib by forming a metal in the groove, forming a photoresist pattern including openings in each of the cell areas, growing a plating film in each of the cell areas, forming a mask membrane formed of the plating film by removing the photoresist pattern, and etching a rear surface of the silicon substrate to form cell openings associated with the cell areas, respectively.

Abstract: A method for manufacturing a deposition mask includes depositing a seed metal layer on a front surface of a silicon substrate, forming a first photoresist pattern defining first openings on the seed metal layer, growing a plating layer in the first openings of the first photoresist pattern, forming a mask membrane by removing the first photoresist pattern and leaving the plating layer, depositing a protection layer to cover a front surface of the mask membrane, forming a second photoresist pattern defining cell opening corresponding to unit masks, respectively, on a back surface of the silicon substrate, exposing the seed metal layer by etching the back surface of the silicon substrate using the second photoresist pattern as a mask, exposing a back surface of the mask membrane by etching the seed metal layer using the second photoresist pattern as a mask, and removing the protection layer.

Abstract: A deposition mask includes a mask body including a silicon substrate, where a plurality of holes is defined through the mask body, and the mask body further includes mask grids extending to define the holes. A cross section of each mask grid has a reverse tapered shape having a width increasing from a back surface to an upper surface of the deposition mask, and each side surface of each mask grid defining a hole includes a first concave curved surface.

Abstract: A semiconductor memory device includes: a memory core including memory cells and configured to output core data stored in the memory cells in response to a read request, a command decoder configured to decode at least one command input from an external device, a command log register configured to sequentially store the at least one command in response to a register enable signal and output the at least one command as a command log in response to a command log read signal, and a mode register set configured to generate the register enable signal or the command log read signal in response to a mode register set command transmitted to the command decoder.

Abstract: A signal receiving device includes a sampling device configured to sample an input signal to output a plurality of sampling values, and an output circuit configured to output data based on the sampling values. The output circuit outputs the data by performing majority voting based on first to third sampling values of the sampling values in response to a first control signal, and outputs the data and first and second error count signals based on the first sampling value and fourth and fifth sampling values of the sampling values in response to a second control signal. The first error count signal is generated by comparing the first sampling value sampled under a reference condition with the fourth sampling value sampled under a first offset condition, and the second error count signal is generated by comparing the first sampling value with the fifth sampling value sampled under a second offset condition.

Abstract: A semiconductor memory device includes: a memory core including memory cells and configured to output core data stored in the memory cells in response to a read request, a command decoder configured to decode at least one command input from an external device, a command log register configured to sequentially store the at least one command in response to a register enable signal and output the at least one command as a command log in response to a command log read signal, and a mode register set configured to generate the register enable signal or the command log read signal in response to a mode register set command transmitted to the command decoder.

Abstract: A signal receiving device includes a sampling device configured to sample an input signal to output a plurality of sampling values, and an output circuit configured to output data based on the sampling values. The output circuit outputs the data by performing majority voting based on first to third sampling values of the sampling values in response to a first control signal, and outputs the data and first and second error count signals based on the first sampling value and fourth and fifth sampling values of the sampling values in response to a second control signal. The first error count signal is generated by comparing the first sampling value sampled under a reference condition with the fourth sampling value sampled under a first offset condition, and the second error count signal is generated by comparing the first sampling value with the fifth sampling value sampled under a second offset condition.

Abstract: A deposition mask unit includes a deposition mask sheet including a plurality of openings, and a deposition mask frame including a raised portion at which the deposition mask sheet is attachable to the deposition mask frame. The raised portion includes a support portion, and a bonding portion protruding from an upper surface of the support portion, an upper surface of the bonding portion being curved.

Abstract: A deposition mask unit includes a deposition mask sheet including a plurality of openings, and a deposition mask frame including a raised portion at which the deposition mask sheet is attachable to the deposition mask frame. The raised portion includes a support portion, and a bonding portion protruding from an upper surface of the support portion, an upper surface of the bonding portion being curved.

Abstract: Disclosed is a method of manufacturing a metal mask. A method of manufacturing a metal mask in accordance with an exemplary embodiment of the present invention includes forming through holes in a plate using a laser, by scanning the laser onto sequentially smaller overlapping portions of the plate.

Abstract: A mask substrate that includes a first area and a second area surrounding the first area is provided. Then, a laser beam is irradiated on the mask substrate to at least partly remove a material of the second area. After that, a physical force is applied to the mask substrate to separate the first area from the mask substrate thereby forming an opening through the mask substrate.

Abstract: A mask manufacturing apparatus includes a laser irradiator, a stage, a frame, and a heat spreader sheet. The laser irradiator divides a laser beam into a plurality of sub-laser beams and irradiates the sub-laser beams to a shadow mask material which is placed over a stage. The frame is disposed over the stage to support the shadow mask material. The heat spreader sheet makes contact with the shadow mask material, absorbs heat generated from the shadow mask material, and dissipates the heat to surroundings of the shadow mask material. Accordingly, the shadow mask material is protected from overheating.

Abstract: A memory device includes an interface unit and a memory unit. The interface unit receives a clock signal, a command signal and a data signal, internally adjusts input impedance based upon at least one of the command signal and the clock signal, and generates internal control signal of the memory device based upon the command signal and data signal. The memory unit performs read/write operations based upon the internal control signal.

Abstract: Disclosed are a method and device for cooperatively sending and receiving power wirelessly. Wireless power charging coverage at the level of data signal transmission can be ensured by establishing one or more modes for transmitting, to a specific terminal, a power transmission signal from any of a plurality of nodes which is (are) not engaged in data transmission, and by matching the phase synchronization of the power transmission signal between the one or more nodes and then transmitting, to the specific terminal, a power transmission signal of which the phase synchronization has been matched by means of the one or more modes.

Abstract: A method and apparatus for operating a UE and a BS to perform contention-based scheduling of downlink signal transmissions are disclosed. The method includes receiving, from at least one of BSs adjacent to the UE, a channel carrying inter-BS contention information for downlink signal transmission in an (n+1)th time unit, n being an integer, broadcasting to the BSs a contention number with a highest priority level among contention numbers extracted from the inter-BS contention information, and receiving a downlink signal from a BS that transmitted inter-BS contention information related to the contention number with the highest priority level in the (n+1)th time unit.

Abstract: A method for transmitting scheduling information in a mobile communication system and a femtocell base station apparatus using the same are provided. Scheduling information can be transmitted using a hierarchical scheduling scheme in which a femtocell base station is allocated resources from a macrocell base station and the femtocell base station then allocates resources to femto users within its own resource region.

Abstract: The method for scheduling, at an MS, data transmission and reception of neighbor BSs adjacent to the MS in a wireless communication system includes receiving number information through a specific downlink channel in a first time unit from each of the neighbor BSs, determining, among the neighbor BSs, a BS which is to transmit and receive data in a second time unit, in a predefined rule, according to the number information and fairness information based on one or more of a number of MSs within a cell served by each of the neighbor BSs and a number of time units that each of the neighbor BSs used previously for data transmission and reception, and transmitting a signal indicating that data transmission and reception in the second time unit are not possible, to the other neighbor BSs excluding the determined BS among the neighbor BSs.

Abstract: A method for managing radio resource of a femto cell includes: providing, by the femto cell, a service to one or more UEs by using most of pre-set radio resource; receiving measurement results from the one or more UEs; determining whether or not one or more neighbor femto cells are closely located nearby based on the measurement results; and if it is determined that neighbor femto cells are closely located nearby, reducing the pre-set radio resource into a small radio resource and providing a service with the small radio resource.

Abstract: Disclosed are a method for transmitting scheduling information in a mobile communication system and a femtocell base station using the method. A femtocell base station transmits scheduling information using a layered scheduling system in which the femtocell base station receives an allocated resource from a macrocell base station, and allocates the resource to femtocell users within a resource region thereof.