Abstract: Disclosed is a packaging sleeve for a full complement needle roller bearing, wherein the packing sleeve is adapted to accommodate at least one set of needles of a full complement needle roller bearing, and wherein the packaging sleeve comprises an outer cylindrical sleeve, wherein a shoulder is arranged on an inner surface of the outer cylindrical sleeve so that the set of needles abut against the shoulder when being arranged in the outer cylindrical sleeve. Furthermore, a packaging sleeve arrangement including such a packaging sleeve and a method for mounting a packaging sleeve are disclosed.

Abstract: Disclosed is a packaging sleeve for a full complement needle roller bearing, wherein the packing sleeve is adapted to accommodate at least one set of needles of a full complement needle roller bearing, and wherein the packaging sleeve comprises an outer cylindrical sleeve, wherein a shoulder is arranged on an inner surface of the outer cylindrical sleeve so that the set of needles abut against the shoulder when being arranged in the outer cylindrical sleeve. Furthermore, a packaging sleeve arrangement including such a packaging sleeve and a method for mounting a packaging sleeve are disclosed.

Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor devices and manufacturing methods for the same. A semiconductor device may include: a substrate; a first active region on the substrate; a first gate structure positioned on the first active region; and a first source and a first drain that are positioned in the first active region and respectively on two sides of the first gate structure, where a size of the first drain is larger than a size of the first source. In forms of the present disclosure, because the size of the first drain is larger than the size of the first source, a current from the first drain to the first source is greater than a current from the first source to the first drain, so that the semiconductor device can make a read current relatively low and a write current relatively high in a static random access memory (SRAM), thereby improving a read margin and a write margin.

Abstract: Anti-fuse structure circuit and method of forming an anti-fuse structure circuit are provided. A substrate is provided, and an anti-fuse is formed on the substrate by forming a first gate structure and a dielectric layer on the substrate and forming conductive plugs respectively in the dielectric layer at two sides of the first gate structure. The dielectric layer covers the first gate structure, and the conductive plugs have a width decreasing from top to bottom. A second gate structure is formed on the substrate. A top surface of the first gate structure is higher than a top surface of the second gate structure. The dielectric layer also covers the second gate structure. The conductive plugs are also located respectively in the dielectric layer at two sides of the second gate structure.

Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor devices and manufacturing methods for the same. A semiconductor device may include: a substrate; a first active region on the substrate; a first gate structure positioned on the first active region; and a first source and a first drain that are positioned in the first active region and respectively on two sides of the first gate structure, where a size of the first drain is larger than a size of the first source. In forms of the present disclosure, because the size of the first drain is larger than the size of the first source, a current from the first drain to the first source is greater than a current from the first source to the first drain, so that the semiconductor device can make a read current relatively low and a write current relatively high in a static random access memory (SRAM), thereby improving a read margin and a write margin.

Abstract: Anti-fuse structure circuit and method of forming an anti-fuse structure circuit are provided. A substrate is provided, and an anti-fuse is formed on the substrate by forming a first gate structure and a dielectric layer on the substrate and forming conductive plugs respectively in the dielectric layer at two sides of the first gate structure. The dielectric layer covers the first gate structure, and the conductive plugs have a width decreasing from top to bottom. A second gate structure is formed on the substrate. A top surface of the first gate structure is higher than a top surface of the second gate structure. The dielectric layer also covers the second gate structure. The conductive plugs are also located respectively in the dielectric layer at two sides of the second gate structure.

Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor devices and manufacturing methods for the same. A semiconductor device may include: a substrate; a first active region on the substrate; a first gate structure positioned on the first active region; and a first source and a first drain that are positioned in the first active region and respectively on two sides of the first gate structure, where a size of the first drain is larger than a size of the first source. In forms of the present disclosure, because the size of the first drain is larger than the size of the first source, a current from the first drain to the first source is greater than a current from the first source to the first drain, so that the semiconductor device can make a read current relatively low and a write current relatively high in a static random access memory (SRAM), thereby improving a read margin and a write margin.

Abstract: The present application discloses an electro-static discharge (ESD) transistor array apparatus, and relates to the field of semiconductor technologies.

Abstract: The present application discloses an electro-static discharge (ESD) transistor array apparatus, and relates to the field of semiconductor technologies.

Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor devices and manufacturing methods for the same. A semiconductor device may include: a substrate; a first active region on the substrate; a first gate structure positioned on the first active region; and a first source and a first drain that are positioned in the first active region and respectively on two sides of the first gate structure, where a size of the first drain is larger than a size of the first source. In forms of the present disclosure, because the size of the first drain is larger than the size of the first source, a current from the first drain to the first source is greater than a current from the first source to the first drain, so that the semiconductor device can make a read current relatively low and a write current relatively high in a static random access memory (SRAM), thereby improving a read margin and a write margin.

Abstract: The present disclosure is directed to a semiconductor device and a manufacturing method thereof, which relate to the field of semiconductor technologies. The semiconductor device includes a fin ESD element. The method includes: providing a substrate structure, where the substrate structure includes a semiconductor substrate, and a semiconductor fin for the fin ESD element and an electrode structure surrounding a part of the semiconductor fin that are on the semiconductor substrate; forming a second dielectric layer on the substrate structure to cover the electrode structure; forming, in the second dielectric layer, a trench extending to a top of the electrode, where the trench is on the electrode and extends along a longitudinal direction of the electrode, and a transverse width of the trench is less than or equal to a transverse width of the top of the electrode; and filling the trench with a metal material, so as to form a metal heat sink that is on the top of the electrode and is coupled to the electrode.

Abstract: A semiconductor structure includes a semiconductor device that includes an active region having a semiconductor fin and a gate structure across the semiconductor fin. The gate structure includes a gate electrode. The semiconductor structure also includes a gate line extending from the gate electrode and a metal wiring that is positioned above the gate line and is electrically connected to the gate line through two or more nodes. The semiconductor structure also includes a first measuring electrode and a second measuring electrode coupled respectively to two ends of the metal wiring, the first measuring electrode disposed closer to the gate electrode than the second measuring electrode. The semiconductor structure is configured to measure the temperature of the semiconductor device. During temperature measurement, the first measurement electrode is coupled to a first potential and the second measurement electrode is coupled to a second potential that is lower than the first potential.

Abstract: A semiconductor structure includes a semiconductor device that includes an active region having a semiconductor fin and a gate structure across the semiconductor fin. The gate structure includes a gate electrode. The semiconductor structure also includes a gate line extending from the gate electrode and a metal wiring that is positioned above the gate line and is electrically connected to the gate line through two or more nodes. The semiconductor structure also includes a first measuring electrode and a second measuring electrode coupled respectively to two ends of the metal wiring, the first measuring electrode disposed closer to the gate electrode than the second measuring electrode. The semiconductor structure is configured to measure the temperature of the semiconductor device. During temperature measurement, the first measurement electrode is coupled to a first potential and the second measurement electrode is coupled to a second potential that is lower than the first potential.

Abstract: The present disclosure is directed to a semiconductor device and a manufacturing method thereof, which relate to the field of semiconductor technologies. The semiconductor device includes a fin ESD element. The method includes: providing a substrate structure, where the substrate structure includes a semiconductor substrate, and a semiconductor fin for the fin ESD element and an electrode structure surrounding a part of the semiconductor fin that are on the semiconductor substrate; forming a second dielectric layer on the substrate structure to cover the electrode structure; forming, in the second dielectric layer, a trench extending to a top of the electrode, where the trench is on the electrode and extends along a longitudinal direction of the electrode, and a transverse width of the trench is less than or equal to a transverse width of the top of the electrode; and filling the trench with a metal material, so as to form a metal heat sink that is on the top of the electrode and is coupled to the electrode.

Abstract: A transistor device may include an n-type transistor. The transistor device may further include a first bias voltage unit, which is electrically connected to the n-type transistor and configured to apply a first positive bias voltage to a drain terminal of the n-type transistor when the n-type transistor is in an off state. The transistor device may further include a second bias voltage unit electrically, which is connected to the n-type transistor and configured to apply a second positive bias voltage to a source terminal of the n-type transistor when the n-type transistor is in the off state.

Abstract: A transistor device may include an n-type transistor. The transistor device may further include a first bias voltage unit, which is electrically connected to the n-type transistor and configured to apply a first positive bias voltage to a drain terminal of the n-type transistor when the n-type transistor is in an off state. The transistor device may further include a second bias voltage unit electrically, which is connected to the n-type transistor and configured to apply a second positive bias voltage to a source terminal of the n-type transistor when the n-type transistor is in the off state.

Abstract: Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase a source-drain saturation current in a write operation and to reduce a source-drain saturation current in a read operation. Read and write margins of the SRAM can be increased.

Abstract: Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a semiconductor substrate including a first groove on one side of a gate structure and a second groove on the other side of the gate structure. The first groove can have a sidewall perpendicular to a surface of the semiconductor substrate. The second groove can have a sidewall protruding toward a channel region under the gate structure. A stressing material can be disposed in the first groove to form a drain region and in the second groove to form a source region. Stress generated in the channel region of the MOS transistor can be asymmetric. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase both read and write margins of the SRAM memory.

Abstract: The present invention discloses a semiconductor device and relates to the semiconductor field. The semiconductor device comprises: a PMOS transistor for processing a input signal, the PMOS transistor comprising a gate and a source, the source being connected to a first voltage source; and a restoring circuit connected to the PMOS transistor for preventing degradation of the PMOS transistor, wherein the restoring circuit makes the gate voltage of the PMOS transistor to be higher than the voltage of the first voltage source, when the input signal is at a high level. According to the semiconductor device of the present invention, a positive bias voltage is applied on the gate of the PMOS transistor through the restoring circuit when the PMOS transistor is turned off, which can accelerate electric parameter recovery for PMOS transistors and therefore improve the performance of PMOS transistors.

Abstract: Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase a source-drain saturation current in a write operation and to reduce a source-drain saturation current in a read operation. Read and write margins of the SRAM can be increased.