Patents by Inventor Junichi Arita

Junichi Arita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6232653
    Abstract: A TSOP type semiconductor device having a LOC structure employing a copper (alloy) type frame prevents resin cracks that occur in a reliability test such as a temperature cycle test. The TSOP type semiconductor device has narrower common inner leads where a resin crack would be likely to occur first, and has a thinner chip.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: May 15, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Naotaka Tanaka, Akihiro Yaguchi, Ryuji Kohno, Kiyomi Kojima, Takeshi Terasaki, Hideo Miura, Junichi Arita, Chikako Imura
  • Patent number: 5869888
    Abstract: A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: February 9, 1999
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System, Ltd.
    Inventors: Kunihiro Tsubosaki, Michio Tanimoto, Kunihiko Nishi, Masahiro Ichitani, Shunji Koike, Kazunari Suzuki, Ryosuke Kimoto, Ichiro Anjoh, Taisei Jin, Akihiko Iwaya, Gen Murakami, Masamichi Ishihara, Junichi Arita
  • Patent number: 5714405
    Abstract: A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: February 3, 1998
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems, Ltd.
    Inventors: Kunihiro Tsubosaki, Michio Tanimoto, Kunihiko Nishi, Masahiro Ichitani, Shunji Koike, Kazunari Suzuki, Ryosuke Kimoto, Ichiro Anjoh, Taisei Jin, Akihiko Iwaya, Gen Murakami, Masamichi Ishihara, Junichi Arita
  • Patent number: 5583375
    Abstract: A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: December 10, 1996
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System, Ltd.
    Inventors: Kunihiro Tsubosaki, Michio Tanimoto, Kunihiko Nishi, Masahiro Ichitani, Shunji Koike, Kazunari Suzuki, Ryosuke Kimoto, Ichiro Anjoh, Taisei Jin, Akihiko Iwaya, Gen Murakami, Masamichi Ishihara, Junichi Arita
  • Patent number: 5571428
    Abstract: A method of producing a leadframe for use in semiconductor devices, comprises the steps of forming a space between leads 1a and 1b which are to be overlapped and welded each other, and welding the leads at a region including the space and melting and cutting off one of the leads. In one of the leads which is melted, cohesion and separation of molten metal occur in the region around the space. As a result, unnecessary portions such as an outer frame used for positioning can be cut off at the same time when the leads are connected by welding. Thus, high precision positioning of a plurality of element leadframes as well as high assembling productivity are achieved.
    Type: Grant
    Filed: April 18, 1995
    Date of Patent: November 5, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Asao Nishimura, Akihiro Yaguchi, Mitsuaki Haneda, Ichiro Anjoh, Junichi Arita, Akihiko Iwaya, Masahiro Ichitani
  • Patent number: 5466888
    Abstract: A packaged semiconductor device has a semiconductor chip and leads formed over the chip with an electrically insulating film interposed therebetween and a packaging material for sealing the chip and the inner lead portions of the leads. The electrically insulating film has such an area as to provide a peripheral portion not covered by parts of the inner lead portions of the leads for strengthening adherence of the electrically insulating film to the packaging material and to the chip. The electrically insulating film has a thickness substantially in a range from 80 .mu.m to 200 .mu.m for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature. A stress absorption film may be formed between the electrically insulating film and the semiconductor chip for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature.
    Type: Grant
    Filed: February 7, 1995
    Date of Patent: November 14, 1995
    Assignees: Hitachi, Ltd., Texas Instruments, Inc.
    Inventors: Lim T. Beng, Chai T. Chong, Masazumi Amagai, Ichiro Anjoh, Junichi Arita, Kunihiro Tsubosaki, Masahiro Ichitani, Darvin Edwards
  • Patent number: 5437915
    Abstract: A method of producing a leadframe for use in semiconductor devices, comprises the steps of forming a space between leads 1a and 1b which are to be overlapped and welded each other, and welding the leads at a region including the space and melting and cutting off one of the leads. In one of the leads which is melted, cohesion and separation of molten metal occur in the region around the space. As a result, unnecessary portions such as an outer frame used for positioning can be cut off at the same time when the leads are connected by welding. Thus, high precision positioning of a plurality of element leadframes as well as high assembling productivity are achieved.
    Type: Grant
    Filed: June 16, 1994
    Date of Patent: August 1, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Asao Nishimura, Akihiro Yaguchi, Mitsuaki Haneda, Ichiro Anjoh, Junichi Arita, Akihiko Iwaya, Masahiro Ichitani
  • Patent number: 5406028
    Abstract: A packaged semiconductor device has a semiconductor chip and leads formed over the chip with an electrically insulating film interposed therebetween and a packaging material for sealing the chip and the inner lead portions of the leads. The electrically insulating film has such an area as to provide a peripheral portion not covered by parts of the inner lead portions of the leads for strengthening adherence of the electrically insulating film to the packaging material and to the chip. The electrically insulating film has a thickness substantially in a range from 80 .mu.m to 200 .mu.m for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature. A stress absorption film may be formed between the electrically insulating film and the semiconductor chip for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature.
    Type: Grant
    Filed: February 18, 1994
    Date of Patent: April 11, 1995
    Assignees: Hitachi, Ltd., Texas Instruments Incorporated
    Inventors: Lim T. Beng, Chai T. Chong, Masazumi Amagai, Ichiro Anjoh, Junichi Arita, Kunihiro Tsubosaki, Masahiro Ichitani, Darvin Edwards
  • Patent number: 5371044
    Abstract: A molding method in which a control plate having a size which is equal to or larger than the width of the outlet port of a supply passage are disposed in a cavity adjacent to the resin supply passage of a mold and thereby, the resin molding can be effected substantially equally at upper and lower sides of the insert comprising a semiconductor device and a lead.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: December 6, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Isamu Yoshida, Junichi Saeki, Shigeharu Tsunoda, Kunihiko Nishi, Ichiro Anjoh, Kenichi Imura, Toshihiro Yasuhara, Junichi Arita, Kazuhiro Sugino
  • Patent number: 5299092
    Abstract: A plastic sealed type semiconductor apparatus includes at least two semiconductor devices which are disposed with a space therebetween in such a manner that circuit forming surfaces oppose each other, and an electric signal lead which is adhered to each of the circuit forming surfaces with an insulating member provided therebetween for electric insulation and which is electrically connected to the semiconductor device by a thin metal wire. The semiconductor devices and the electric signal leads are sealed with a resin in a state where the electric signal leads are laid on top of one another to form a plastic package. The overlaid portion of the electric signal leads has a surface contact portion of the leads and a resin providing portion. The resin providing portion is a recessed portion which is formed when the resin is molded in such a manner that it passes through the surface contact portion of the leads in the lateral direction thereof.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: March 29, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Yaguchi, Asao Nishimura, Makoto Kitano, Ichiro Anjoh, Junichi Arita
  • Patent number: 5252854
    Abstract: Disclosed is a resin-molded type semiconductor device having a thin package while avoiding short-circuit of wires with a common inner lead. In the construction thereof, a common inner lead constituted by a thin metal sheet is fixed onto a circuit-forming surface of a rectangular semiconductor chip substantially in parallel with longer sides of the chip and substantially in a central region of the chip, and a plurality of inner leads for signals, which are in the form of a frame, are stacked and fixed onto the common inner lead; then these components are molded with resin.
    Type: Grant
    Filed: June 18, 1991
    Date of Patent: October 12, 1993
    Assignees: Hitachi, Ltd., Hitachi Microcomputer
    Inventors: Junichi Arita, Akihiko Iwaya, Tomoo Matsuzawa, Masahiro Ichitani