Abstract: A clock signal control system of the present invention includes a simple circuit for generating a clock stop signal. With this circuit, the system is small size and easy to design and consumes a minimum of power.

Abstract: In a digital processor having a plurality of memories and a plurality of ALUs, each of address ports of each of the memories is associated with an address generation circuit capable of executing a loop processing required for address generation. With this arrangement, it is possible to access a plurality of memories, and therefore, the processing efficiency is improved.

Abstract: A test circuit for conducting a simultaneous test of a plurality of integrated circuits provided in dicing regions of a wafer. The test circuit has a pattern generator electrically connected to the integrated circuits through first interconnections for generating input signal patterns and subsequent transmission thereof to each of the integrated circuits and pattern compressor/comparator electrically connected to the integrated circuits through second interconnections for analyzing output signals fetched from the integrated circuits so as to conduct a simultaneous test of a plurality of the integrated circuits.

Abstract: A digital processor has a data processing unit having arithmetic/logic operation circuits, an instruction memory for storing an instruction word, and an instruction decoder for decoding the instruction word read from the instruction memory and outputting the control signals respectively to the arithmetic/logic operation circuits. Each instruction word has at least a first control field and a second control field. The instruction decoder has two decoding circuits. Each of the decoding circuits corresponds to each group of the arithmetic/logic operation circuits, receives the instruction word for decoding the second control field into a control signal and outputs an ENABLE signal. The ENABLE signal from the first decoding circuit is applied to the second decoding circuit, and the ENABLE signal from the second decoding circuit is applied to the first decoding circuit. Only one of the first and second decoding circuits outputs a control signal at a time.

Abstract: A resin composition comprising a polyester and a modified polyolefin, wherein said polyester has an amide bond in polymer main chain and said modified polyolefin has a carboxylic acid group or a derivative thereof.

Abstract: A polyurethane polyol obtained by reacting a hydrocarbon diol of the formula (A):HO--R--OH (A)wherein R is a C.sub.7-20 linear or branched alkylene group, with isophorone diisocyanate and having a number average molecular weight of from 500 to 20,000.

Abstract: In a method for manufacturing a semiconductor memory device, a semiconductor chip and an adhesive tape having an adhesive layer are prepared. The adhesive layer comprises a polyamic acid intermediate derived for example from a pyromellitic dianhydride and a diamine. The adhesive tape is pressed onto the semiconductor chip at a temperature of from about 250.degree. C. to about 400.degree. C. for a predetermined time period such as 2 to 5 sec.