Patents by Inventor Junichi Hibino

Junichi Hibino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10406681
    Abstract: A robot includes: a restricting member configured to restrict a horizontal movement of a predetermined workpiece; and a workpiece moving member configured to generate an action for horizontally moving the workpiece. The controller performs a control operation of positioning the workpiece at a stop position in such a manner that: based on predetermined size information of the workpiece and preset stop position information of the workpiece, the restricting member is positioned at a predetermined restricting position included in the stop position for the workpiece, and the workpiece moving member acts on the workpiece and is moved toward the restricting position to horizontally move the workpiece; and the workpiece is brought into contact with the restricting member.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: September 10, 2019
    Assignee: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Junichi Murakami, Kenji Bando, Yukio Iwasaki, Satoru Hibino, Yoshiaki Tanaka, Yasuhiko Hashimoto, Takahiro Inada
  • Patent number: 10388986
    Abstract: A sulfide solid electrolyte material includes a sulfide phase containing a sulfide material and an oxide phase containing an oxide formed by oxidation of the sulfide material. The oxide phase is located on a surface of the sulfide phase. The sulfide solid electrolyte material satisfies conditions: 1.28?x?4.06 and x/y?2.60, where x denotes the oxygen-to-sulfur elemental ratio measured by XPS depth profiling at the outermost surface of the oxide phase; and y denotes the oxygen-to-sulfur elemental ratio measured by XPS depth profiling at a position 32 nm, estimated from the SiO2 sputtering rate, away from the outermost surface of the oxide phase.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: August 20, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Izuru Sasaki, Junichi Hibino
  • Patent number: 10338597
    Abstract: A self-traveling articulated robot for working in a production factory is provided, which includes a carriage having at least two operation shafts driven by servomotors, respectively, and self-travelable in a two-dimensional plane, a robotic arm supported by the carriage and having at least one operation shaft driven by a servomotor and constituting a joint, an end effector provided to a tip portion of the robotic arm, and a control unit provided in the carriage and for controlling the operation shaft of the robotic arm and the operation shafts of the carriage to operate in cooperation with each other so that a control point defined in one of the robotic arm and the end effector reaches a target position.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: July 2, 2019
    Assignee: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Yasuhiko Hashimoto, Takahiro Inada, Kenji Bando, Yoshiaki Tanaka, Junichi Murakami, Satoru Hibino, Yukio Iwasaki
  • Publication number: 20190198922
    Abstract: A battery includes a first positive electrode collector, a first negative electrode collector, a first power generating element, a second power generating element, and a first insulating part. The first and second power generating elements each include a positive electrode active material-containing layer, a negative electrode active material-containing layer, and an inorganic solid electrolyte-containing layer. In each of the first and second power generating elements, the inorganic solid electrolyte layer is in contact with the positive electrode active material-containing layer and the negative electrode active material-containing layer. The positive electrode active material layers of the first and second power generating elements are in contact with the first positive electrode collector. The negative electrode active material layers of the first and second power generating elements are in indirect contact with the first negative electrode collector.
    Type: Application
    Filed: March 6, 2019
    Publication date: June 27, 2019
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Izuru SASAKI, Junichi HIBINO
  • Patent number: 10270125
    Abstract: Provided is a battery including a first positive electrode collector, a first negative electrode collector, a first power generating element, a second power generating element, and a first insulating part. The first and second power generating elements each include a positive electrode active material-containing layer, a negative electrode active material-containing layer, and an inorganic solid electrolyte-containing layer. In each of the first and second power generating elements, the inorganic solid electrolyte layer is in contact with the positive electrode active material-containing layer and the negative electrode active material-containing layer. The positive electrode active material layers of the first and second power generating elements are in contact with the first positive electrode collector. The negative electrode active material layers of the first and second power generating elements are in contact with the first negative electrode collector.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: April 23, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Izuru Sasaki, Junichi Hibino
  • Publication number: 20170331149
    Abstract: A sulfide solid electrolyte material includes a sulfide phase containing a sulfide material and an oxide phase containing an oxide formed by oxidation of the sulfide material. The oxide phase is located on a surface of the sulfide phase. The sulfide solid electrolyte material satisfies conditions: 1.28?x?4.06 and x/y?2.60, where x denotes the oxygen-to-sulfur elemental ratio measured by XPS depth profiling at the outermost surface of the oxide phase; and y denotes the oxygen-to-sulfur elemental ratio measured by XPS depth profiling at a position 32 nm, estimated from the SiO2 sputtering rate, away from the outermost surface of the oxide phase.
    Type: Application
    Filed: April 11, 2017
    Publication date: November 16, 2017
    Inventors: IZURU SASAKI, JUNICHI HIBINO
  • Publication number: 20160315346
    Abstract: Provided is a battery including a first positive electrode collector, a first negative electrode collector, a first power generating element, a second power generating element, and a first insulating part. The first and second power generating elements each include a positive electrode active material-containing layer, a negative electrode active material-containing layer, and an inorganic solid electrolyte-containing layer. In each of the first and second power generating elements, the inorganic solid electrolyte layer is in contact with the positive electrode active material-containing layer and the negative electrode active material-containing layer. The positive electrode active material layers of the first and second power generating elements are in contact with the first positive electrode collector. The negative electrode active material layers of the first and second power generating elements are in contact with the first negative electrode collector.
    Type: Application
    Filed: March 17, 2016
    Publication date: October 27, 2016
    Inventors: Izuru SASAKI, Junichi HIBINO
  • Patent number: 9142748
    Abstract: A light emitting device in which a plurality of LED chips are arranged. Each of the plurality of LED chips include a light emitting region that is formed on a substrate, a first pad electrode that is formed on the substrate, and a through-hole that penetrates the substrate. First wiring that passes through the through-hole of one LED chip and the through-hole of an adjacent LED chip, and electrically connects the first pad electrode of the one LED chip and the first pad electrode of the adjacent LED chip is provided. The tip-end parts of the first wiring that have passed through the through-holes have, at a cross section cut at a plane that is parallel with a principal surface of the substrate, a larger cross-sectional area than the cross-sectional area of the first wiring inside the through-holes.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: September 22, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideki Ohmae, Junichi Hibino, Atsushi Yamada
  • Publication number: 20150214197
    Abstract: A light-emitting device includes: a plurality of LED chips each having a light-emitting region, and a first electrode and a second electrode that are electrically connected to light-emitting region; a plurality of substrates each being provided on each of the plurality of LED chips; a plurality of through-holes each penetrating through each of the plurality of substrates; and, a plurality of wires each passing through a first through-hole penetrated through a first substrate of the plurality of the substrates and a second through-hole penetrated through a second substrate adjacent to the first substrate. The one of the plurality of the wires is electrically connected the first electrode or the second electrode of a first LED chip corresponding to the first substrate, to the first electrode or the second electrode of a second LED chip corresponding to the second substrate.
    Type: Application
    Filed: April 1, 2015
    Publication date: July 30, 2015
    Inventors: HIDEKI OHMAE, JUNICHI HIBINO, ATSUSHI YAMADA, DAISUKE UEDA
  • Publication number: 20150179905
    Abstract: A light emitting device in which a plurality of LED chips are arranged. Each of the plurality of LED chips include a light emitting region that is formed on a substrate, a first pad electrode that is formed on the substrate, and a through-hole that penetrates the substrate. First wiring that passes through the through-hole of one LED chip and the through-hole of an adjacent LED chip, and electrically connects the first pad electrode of the one LED chip and the first pad electrode of the adjacent LED chip is provided. The tip-end parts of the first wiring that have passed through the through-holes have, at a cross section cut at a plane that is parallel with a principal surface of the substrate, a larger cross-sectional area than the cross-sectional area of the first wiring inside the through-holes.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 25, 2015
    Inventors: HIDEKI OHMAE, JUNICHI HIBINO, ATSUSHI YAMADA
  • Patent number: 8035301
    Abstract: A plasma display device having a panel main body in which a pair of transparent substrates is arranged in opposition so as to form a discharge space between the substrates on at least a front side, barrier ribs are arranged on at least one of the substrates to divide the discharge space into a plurality of spaces, a group of electrodes is arranged on the substrates so as to generate discharge in the discharge space divided with the barrier ribs, and phosphor layers that emit by discharge are provided, in which the phosphor layers are equipped with a green phosphor layer including at least Zn2SiO4:Mn, a surface of Zn2SiO4:Mn is coated with magnesium oxide, and a ratio of an Mg element to a Si element on the surface measured with an XPS apparatus is 0.7 to 4.0.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: October 11, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshihisa Nagasaki, Izumi Toyoda, Junichi Hibino, Kazuhiko Sugimoto, Keiji Horikawa, Nobuyuki Shigetoh, Yuichiro Miyamae
  • Patent number: 7911139
    Abstract: A plasma display device has a panel main body in which a pair of transparent substrates is arranged in opposition so as to form a discharge space between the substrates on at least a front side. Barrier ribs are arranged on at least one of the substrates to divide the discharge space into a plurality of spaces. A group of electrodes is arranged on the substrates so as to generate discharge in the discharge space divided with the barrier ribs. Phosphor layers that emit by discharge are also provided. The phosphor layers are equipped with a green phosphor layer including at least Zn2SiO4:Mn, a surface of Zn2SiO4:Mn is coated with aluminum oxide, and a ratio of an Al element to a Si element on the surface measured with an XPS apparatus is 0.6 to 4.0.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: March 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshihisa Nagasaki, Izumi Toyoda, Junichi Hibino, Kazuhiko Sugimoto, Keiji Horikawa, Nobuyuki Shigetoh, Yuichiro Miyamae
  • Publication number: 20100156266
    Abstract: A gas discharge light emitting panel is provided that prevents deterioration in display properties of the panel, which accompanies changes in light-emitting properties of phosphors. It includes a front panel and a rear panel that are disposed to oppose each other, with a discharge space being interposed therebetween, and a phosphor layer that is disposed above a principal surface located on the discharge space side of the rear panel and that emits light by being irradiated with ultraviolet rays generated in the discharge space. The phosphor layer contains first and second phosphors in which the changes in at least one property selected from luminance and chromaticity, which accompany driving of the panel, occur in the opposite directions to each other.
    Type: Application
    Filed: July 26, 2006
    Publication date: June 24, 2010
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takehiro Zukawa, Seigo Shiraishi, Kojiro Okuyama, Junichi Hibino, Keiji Horikawa
  • Patent number: 7728795
    Abstract: Set-up, write, sustain and erase pulses are variously applied to a plasma display panel using a staircase waveform in which the rising or falling portion is in at least two steps. These staircase waveforms can be realized by adding at least two pulses. Use of such waveforms for the set-up, write and erase pulses improves contrast, and use for the sustain pulses reduces screen flicker and improves luminous efficiency. This is of particular use in driving high definition plasma display panels to achieve high image quality and high luminance.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: June 1, 2010
    Assignee: Panasonic Corporation
    Inventors: Nobuaki Nagao, Hidetaka Higashino, Junichi Hibino
  • Patent number: 7728794
    Abstract: Set-up, write, sustain and erase pulses are variously applied to a plasma display panel using a staircase waveform in which the rising or falling portion is in at least two steps. These staircase waveforms can be realized by adding at least two pulses. Use of such waveforms for the set-up, write and erase pulses improves contrast, and use for the sustain pulses reduces screen flicker and improves luminous efficiency. This is of particular use in driving high definition plasma display panels to achieve high image quality and high luminance.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: June 1, 2010
    Assignee: Panasonic Corporation
    Inventors: Nobuaki Nagao, Hidetaka Higashino, Junichi Hibino
  • Patent number: 7728793
    Abstract: Set-up, write, sustain and erase pulses are variously applied to a plasma display panel using a staircase waveform in which the rising or falling portion is in at least two steps. These staircase waveforms can be realized by adding at least two pulses. Use of such waveforms for the set-up, write and erase pulses improves contrast, and use for the sustain pulses reduces screen flicker and improves luminous efficiency. This is of particular use in driving high definition plasma display panels to achieve high image quality and high luminance.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: June 1, 2010
    Assignee: Panasonic Corporation
    Inventors: Nobuaki Nagao, Hidetaka Higashino, Junichi Hibino
  • Patent number: 7724214
    Abstract: Set-up, write, sustain and erase pulses are variously applied to a plasma display panel using a staircase waveform in which the rising or falling portion is in at least two steps. These staircase waveforms can be realized by adding at least two pulses. Use of such waveforms for the set-up, write and erase pulses improves contrast, and use for the sustain pulses reduces screen flicker and improves luminous efficiency. This is of particular use in driving high definition plasma display panels to achieve high image quality and high luminance.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: May 25, 2010
    Assignee: Panasonic Corporation
    Inventors: Nobuaki Nagao, Hidetaka Higashino, Junichi Hibino
  • Patent number: 7705537
    Abstract: A plasma display device having a panel main body in which a pair of transparent substrates is arranged in opposition so as to form a discharge space between the substrates on at least a front side, barrier ribs are arranged on at least one of the substrates to divide the discharge space into a plurality of spaces, a group of electrodes is arranged on the substrates so as to generate discharge in the discharge space divided with the barrier ribs, and phosphor layers that emit by discharge are provided, in which the phosphor layers are equipped with a green phosphor layer including at least a mixture of Zn2SiO4:Mn and (Y, Gd)BO3:Tb, the surface of the Zn2SiO4:Mn is coated with aluminum oxide, and the ratio of the Al element to the Si element on the surface measured with an XPS apparatus is 0.6 to 7.0.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: April 27, 2010
    Assignee: Panasonic Corporation
    Inventors: Izumi Toyoda, Yoshihisa Nagasaki, Junichi Hibino, Kazuhiko Sugimoto, Keiji Horikawa, Nobuyuki Shigetoh, Yuichiro Miyamae
  • Patent number: 7705807
    Abstract: Set-up, write, sustain and erase pulses are variously applied to a plasma display panel using a staircase waveform in which the rising or falling portion is in at least two steps. These staircase waveforms can be realized by adding at least two pulses. Use of such waveforms for the set-up, write and erase pulses improves contrast, and use for the sustain pulses reduces screen flicker and improves luminous efficiency. This is of particular use in driving high definition plasma display panels to achieve high image quality and high luminance.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: April 27, 2010
    Assignee: Panasonic Corporation
    Inventors: Nobuaki Nagao, Hidetaka Higashino, Junichi Hibino
  • Patent number: RE41465
    Abstract: A plasma display device has a first plate and a second plate which face each other with a discharge space therebetween, and a sealing member which is provided between the first and second plates to seal the discharge space at edges of the first and second plates. A plurality of electrodes are formed on the inner major surface of the first or second plate. An electrode diffusion preventive layer is formed in each area where the plurality of electrodes cross over the sealing member, so as to avoid direct contact between the plurality of electrodes and the sealing member. As a result, problems such as breaking of the electrodes can be avoided. This construction is especially effective when the electrodes contain Ag.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: August 3, 2010
    Assignee: Panasonic Corporation
    Inventors: Katsuyoshi Yamashita, Yoshiki Sasaki, Junichi Hibino, Masafumi Ookawa, Masaki Aoki