Patents by Inventor Junichi Saeki

Junichi Saeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8095348
    Abstract: A model creation portion having a obstacle in a space includes two creation portions, one is to separate them and another is to combine them which handles, as porous media, an obstacle in which narrow spaces are regularly arranged. A thermosets flow analysis portion includes two analysis portions to separate and combine them, each of them has a viscosity equation for thermosets. The space/obstacle separation analysis portion analyzes by combining the viscosity equation with conservation equations of mass, momentum and energy, and the space/obstacle combination analysis portion analyzes by combining the viscosity equation with a conservation equation directed to a shape simplified as porous media. Resin flow behavior is analyzed while data in an interface between two models is delivered to each other, to accurately predict filling behavior at the time of injecting resin of thermosets molded articles having the complex obstacles.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: January 10, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Saeki, Tsutomu Kono
  • Publication number: 20080234989
    Abstract: To quick and accurately predict filling behavior at the time of injecting resin of thermosets molded articles having a complex obstacle. A model creation portion includes a space/obstacle separation model creation portion and a space/obstacle combination model creation portion. The space/obstacle combination model creation portion handles, as porous media, an obstacle in which narrow spaces are regularly arranged. A thermosets flow analysis portion includes a space/obstacle separation analysis portion and a space/obstacle combination analysis portion, and each of them has a viscosity equation for thermosets. The space/obstacle separation analysis portion analyzes by combining the viscosity equation with conservation equations of mass, momentum and energy, and the space/obstacle combination analysis portion analyzes by combining the viscosity equation with a conservation equation directed to a shape simplified as porous media.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 25, 2008
    Inventors: Junichi Saeki, Tsutomu Kono
  • Patent number: 7277771
    Abstract: To regulate the passage structure of a foaming die and the injected amount of foaming material, the flow behavior of the foaming material is analyzed by obtaining a flow velocity and a pressure by inputting the density as a function, including the elapsed time from the passage through an injection port to the foaming die and the thickness, and substituting a calculated density in equations of continuity and motion. In the analysis, the viscosity of the foaming material is used as a function including a time term. The boundary and molding conditions are corrected when the calculation does not converge. The density and pressure distributions of the foaming material are determined when the calculation converges. When the density and pressure distributions depart from design tolerances, the foaming passage structure and foaming material injected amount are regulated by an analysis program that corrects the model form, physical property or molding condition.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: October 2, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Kono, Junichi Saeki
  • Patent number: 7096083
    Abstract: A design support apparatus including: a flow analyzer for analyzing a flow of thermosetting resin injected into a resin filling cavity to mold a resin mold product made of the thermosetting resin, using a finite difference method or a finite element method; a residual strain calculator for calculating residual strain (or stress) of the thermosetting resin after heat shrinkage of the thermosetting resin injected into the resin filling cavity to mold the resin mold product; and a strength analyzer for analyzing strength of the resin mold product, using a finite element method. According to this arrangement, strength of the resin mold product made of the thermosetting resin can be predicted accurately.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: August 22, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Osami Kaneto, Toshiya Teramae, Junichi Saeki
  • Patent number: 7023027
    Abstract: A small semiconductor package having two electrodes, which can be produced at reduced cost and which features high reliability. The package has a structure in which an anode and a cathode are arranged on one surface of a semiconductor chip, each electrode having a bump electrode for connecting the electrode to an external substrate. An insulating resin is provided on the surface of the semiconductor chip and on the surfaces of the bump electrodes, except at least for the connection portions to the external substrate.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: April 4, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Toshiya Teramae, Junichi Saeki, Yasuharu Ichinose, Shuichi Suzuki
  • Publication number: 20060004481
    Abstract: To regulate the passage structure of a foaming die and the injected amount of foaming material, the flow behavior of the foaming material is analyzed by obtaining a flow velocity and a pressure by inputting the density as a function, including the elapsed time from the passage through an injection port to the foaming die and the thickness, and substituting a calculated density in equations of continuity and motion. In the analysis, the viscosity of the foaming material is used as a function including a time term. The boundary and molding conditions are corrected when the calculation does not converge. The density and pressure distributions of the foaming material are determined when the calculation converges. When the density and pressure distributions depart from design tolerances, the foaming passage structure and foaming material injected amount are regulated by an analysis program that corrects the model form, physical property or molding condition.
    Type: Application
    Filed: June 16, 2005
    Publication date: January 5, 2006
    Inventors: Tsutomu Kono, Junichi Saeki
  • Patent number: 6919622
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: July 19, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6861294
    Abstract: A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: March 1, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Shigeharu Tsunoda, Junichi Saeki, Isamu Yoshida, Kazuya Ooji, Michiharu Honda, Makoto Kitano, Nae Yoneda, Shuji Eguchi, Kunihiko Nishi, Ichiro Anjoh, Kenichi Otsuka
  • Patent number: 6844219
    Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: January 18, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Makoto Kitano, Akihiro Yaguchi, Naotaka Tanaka, Takeshi Terasaki, Ichiro Anjoh, Ryo Haruta, Asao Nishimura, Junichi Saeki
  • Publication number: 20040155323
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Application
    Filed: February 10, 2004
    Publication date: August 12, 2004
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Publication number: 20040093104
    Abstract: A design support apparatus comprises: a flow analysis means for analyzing a flow of thermosetting resin injected into a resin filling cavity to mold a resin mold product made of the thermosetting resin, using a finite difference method or a finite element method; a residual strain calculation means for calculating residual strain (or stress) of the thermosetting resin after heat shrinkage of the thermosetting resin injected into the resin filling cavity to mold said resin mold product; and a strength analysis means for analyzing strength of said resin mold product, using a finite element method. According to this arrangement, strength of the resin mold product made of the thermosetting resin can be predicted accurately.
    Type: Application
    Filed: July 29, 2003
    Publication date: May 13, 2004
    Inventors: Osami Kaneto, Toshiya Teramae, Junichi Saeki
  • Patent number: 6720208
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: April 13, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Publication number: 20040063272
    Abstract: A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 1, 2004
    Applicant: HITACHI, LTD.
    Inventors: Shigeharu Tsunoda, Junichi Saeki, Isamu Yoshida, Kazuya Ooji, Michiharu Honda, Makoto Kitano, Nae Yoneda, Shuji Eguchi, Kunihiko Nishi, Ichiro Anjoh, Kenichi Otsuka
  • Patent number: 6686226
    Abstract: A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold, which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: February 3, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Shigeharu Tsunoda, Junichi Saeki, Isamu Yoshida, Kazuya Ooji, Michiharu Honda, Makoto Kitano, Nae Yoneda, Shuji Eguchi, Kunihiko Nishi, Ichiro Anjoh, Kenichi Otsuka
  • Publication number: 20030127712
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Application
    Filed: December 19, 2002
    Publication date: July 10, 2003
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Publication number: 20030094621
    Abstract: A small semiconductor package having two electrodes suppressing the cost and featuring high reliability. The package has a structure in which an anode and a cathode are arranged on one surface of a semiconductor chip, each electrode having a bump electrode for connecting the electrode to an external substrate. An insulating resin is provided on the surface of the semiconductor chip and on the surfaces of the bump electrodes except at least the connection portions to the external substrate.
    Type: Application
    Filed: November 15, 2002
    Publication date: May 22, 2003
    Inventors: Toshiya Teramae, Junichi Saeki, Yasuharu Ichinose, Shuichi Suzuki
  • Patent number: 6531760
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: March 11, 2003
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6465876
    Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bond ed to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Akihiro Yaguchi, Naotaka Tanaka, Takeshi Terasaki, Ichiro Anjoh, Ryo Haruta, Asao Nishimura, Junichi Saeki
  • Publication number: 20020135051
    Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.
    Type: Application
    Filed: May 2, 2002
    Publication date: September 26, 2002
    Inventors: Asao Nishimura, Junichi Saeki
  • Patent number: 6326681
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: December 4, 2001
    Assignee: Hitachi, LTD
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto