Patents by Inventor Junichi Wada

Junichi Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140070289
    Abstract: According to one embodiment, a ferroelectric memory includes a gate insulation film formed on a semiconductor substrate, a ferroelectric film formed on the gate insulation film, and a control electrode formed on the ferroelectric film. The ferroelectric film is a film containing a metal, which is hafnium or zirconium, and oxygen, and contains an element other than the metal at a concentration lower than a concentration of the metal.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 13, 2014
    Inventors: Masayuki TANAKA, Junichi WADA, Yoshio OZAWA, Koji YAMAKAWA, Seiji INUMIYA, Atsuko SAKATA
  • Publication number: 20140021430
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer
    Type: Application
    Filed: September 27, 2013
    Publication date: January 23, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Patent number: 8569728
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Publication number: 20130248808
    Abstract: A resistance change element includes a first conductive layer, a second conductive layer, and a memory layer. The memory layer is provided between the first conductive layer and the second conductive layer. The memory layer is capable of reversibly transitioning between a first state and a second state due to at least one of a voltage and a current supplied via the first conductive layer and the second conductive layer. A resistance of the second state is higher than a resistance of the first state. The memory layer includes niobium oxide. One of a (100) plane, a (010) plane, and a (110) plane of the memory layer is oriented in a stacking direction from the first conductive layer toward the second conductive layer.
    Type: Application
    Filed: February 28, 2013
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noritake OOMACHI, Junichi WADA, Kouji MATSUO, Tomotaka ARIGA, Yoshio OZAWA
  • Publication number: 20130243680
    Abstract: A group 13 nitride crystal has a hexagonal crystal structure containing a nitrogen atom and at least one type of metal atom selected from the group consisting of B, Al, Ga, In, and Tl. The group 13 nitride crystal has a basal plane dislocation in a plurality of directions. Dislocation density of the basal plane dislocation is higher than dislocation density of a threading dislocation of a c-plane.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 19, 2013
    Applicant: RICOH COMPANY, LITD.
    Inventors: Masahiro HAYASHI, Seiji SARAYAMA, Takashi SATOH, Chiharu KIMURA, Naoya MIYOSHI, Akishige MURAKAMI, Junichi WADA
  • Publication number: 20130240822
    Abstract: A nonvolatile memory device includes a first film layer formed on a substrate, and a second film layer formed on the first film layer. The second film layer comprises a first oxide material having a first oxygen content, and a second oxide material disposed laterally of the first oxide material and having a second oxygen content that is greater than the first oxygen content. The memory device also includes a third film layer formed on the second film layer, and the third film layer is disposed on the first oxide material and exposes portions of the second oxide material.
    Type: Application
    Filed: September 7, 2012
    Publication date: September 19, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Junichi WADA
  • Patent number: 8537594
    Abstract: According to one embodiment, a resistance change element includes a first film provided on a first electrode side, a second film provided on a second electrode side, a barrier film sandwiched between the first film and the second film, and metal impurities added in the first or second film, the metal impurities migrating between the first and second films bi-directionally according to a direction of a first electric field generated between the first and second electrodes. The resistance change element has a first resistance state when the metal impurities are present in the first film, and the resistance change element has a second resistance state different from the first resistance state when the metal impurities are present in the second film.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junichi Wada
  • Patent number: 8410467
    Abstract: According to one embodiment, a nonvolatile memory device includes a first wire, a second wire and a nonvolatile memory cell. The first wire is formed to extend in a first direction, and the second wire is formed at height different from height of the first wire and to extend in a second direction. The nonvolatile memory cell is arranged to be held between the first wire and the second wire in a poison where the first wire and the second wire cross. The nonvolatile memory cell includes a nonvolatile storage layer and a current limiting resistance layer connected in series to the nonvolatile storage layer and having resistance of 1 kilo-ohm to 1 mega-ohm.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: April 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junichi Wada
  • Publication number: 20120306081
    Abstract: According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.
    Type: Application
    Filed: March 22, 2012
    Publication date: December 6, 2012
    Inventors: Takeshi ISHIZAKI, Atsuko Sakata, Junichi Wada, Masahiko Hasunuma
  • Publication number: 20120292587
    Abstract: According to one embodiment, a nonvolatile memory device includes a memory cell. The memory cell includes a stacked film structure. The stacked film structure is capable of maintaining a first state or a second state. The first state includes a lower electrode film, a first memory element film provided on the lower electrode film and containing a first oxide and an upper electrode film provided on the first memory element film. The second state includes the lower electrode film, the first memory element film provided on the lower electrode film, a second memory element film provided on the first memory element film and containing a second oxide and the upper electrode film provided on the second memory element film.
    Type: Application
    Filed: March 20, 2012
    Publication date: November 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kouji MATSUO, Noritake OHMACHI, Tomotaka ARIGA, Junichi WADA, Yoshio OZAWA
  • Publication number: 20120152168
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 21, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Patent number: 8148274
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Wada, Atsuko Sakata, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Publication number: 20120069625
    Abstract: According to one embodiment, a resistance change element includes a first film provided on a first electrode side, a second film provided on a second electrode side, a barrier film sandwiched between the first film and the second film, and metal impurities added in the first or second film, the metal impurities migrating between the first and second films bi-directionally according to a direction of a first electric field generated between the first and second electrodes. The resistance change element has a first resistance state when the metal impurities are present in the first film, and the resistance change element has a second resistance state different from the first resistance state when the metal impurities are present in the second film.
    Type: Application
    Filed: July 5, 2011
    Publication date: March 22, 2012
    Inventor: Junichi WADA
  • Patent number: 7994054
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a first metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, oxidizing at least part of the first metal film with oxidizing species remaining in the insulating film, and forming a second metal film, which includes any of a high melting point metal and a noble metal, on the first metal film, the first metal film and the second metal film sharing different metallic material.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Patent number: 7996813
    Abstract: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Hatano, Motoya Okazaki, Junichi Wada, Takeshi Nishioka, Hisashi Kaneko, Takeshi Fujimaki, Kazuyuki Higashi, Kenji Yoshida, Noriaki Matsunaga
  • Patent number: 7982575
    Abstract: An ignition coil, which includes a primary coil and a secondary coil, has an electrical insulating member. The electrical insulating member includes an insulating material being a base material. The electrical insulating member further includes a reactive agent being an additive added to the insulating material for causing dehydration-decomposition, so as to enhance durability when being applied with high voltage. Alternatively, a reactive agent is coated on a surface of the electrical insulating body for causing dehydration-decomposition, so as to enhance durability when being applied with high voltage.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: July 19, 2011
    Assignee: Denso Corporation
    Inventors: Junichi Wada, Junji Shirai
  • Patent number: 7923839
    Abstract: A semiconductor device includes a contact plug electrically connected to a semiconductor substrate; a first barrier metal film with a columnar crystal structure arranged in contact with the semiconductor substrate at least on a bottom surface side of the contact plug; an amorphous film made of a material of the first barrier metal film arranged in contact with the first barrier metal film at least on the bottom surface side of the contact plug; a second barrier metal film made of a material identical to that of the first barrier metal film and having a columnar crystal structure, at least a portion of which is arranged in contact with the amorphous film on the bottom surface side and a side surface side of the contact plug; and a dielectric film arranged on the side surface side of the contact plug.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: April 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Kitamura, Junichi Wada, Hideto Matsuyama
  • Patent number: 7907040
    Abstract: An ignition coil includes a coil body, a primary resin molded body, and a secondary resin molded body. The coil body has a primary coil and a secondary coil. The primary resin molded body has the coil body therein in a fixed relation, and the primary resin molded body has a plurality of exposed side portions that hold the coil body therebetween. The secondary resin molded body is molded to have the coil body and the primary resin molded body embedded therein. The secondary resin molded body is configured to allow the plurality of exposed side portions of the primary resin molded body to be exposed to an exterior of the secondary resin molded body.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: March 15, 2011
    Assignee: Denso Corporation
    Inventor: Junichi Wada
  • Publication number: 20110037043
    Abstract: According to one embodiment, a nonvolatile memory device includes a first wire, a second wire and a nonvolatile memory cell. The first wire is formed to extend in a first direction, and the second wire is formed at height different from height of the first wire and to extend in a second direction. The nonvolatile memory cell is arranged to be held between the first wire and the second wire in a poison where the first wire and the second wire cross. The nonvolatile memory cell includes a nonvolatile storage layer and a current limiting resistance layer connected in series to the nonvolatile storage layer and having resistance of 1 kilo-ohm to 1 mega-ohm.
    Type: Application
    Filed: June 11, 2010
    Publication date: February 17, 2011
    Inventor: Junichi WADA
  • Publication number: 20110031622
    Abstract: A method for fabricating a semiconductor device according to an embodiment includes: forming a nickel (Ni) film containing phosphorus (P) elements on a substrate having at least one of a diffusion layer formed by using silicon (Si) and a gate electrode formed by using Si exposed on a surface thereof; and forming a nickel silicide (NiSi) film containing P elements on the substrate from the Ni film containing the P elements and Si in at least one of the diffusion layer and the gate electrode.
    Type: Application
    Filed: August 9, 2010
    Publication date: February 10, 2011
    Inventors: Makoto HONDA, Junichi Wada