Patents by Inventor Junichi Yamada

Junichi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210134930
    Abstract: A frame region includes a first routed wire extending from one of a plurality of scan signal lines, one of a plurality of light-emission control lines, or one of a plurality of data signal lines. The first routed wire is electrically connected to drive circuits. The first routed wire is included in a first metal layer. A first conductive film is included in a second metal layer. The first routed wire and the first conductive film overlap each other via an inorganic insulating film.
    Type: Application
    Filed: March 30, 2018
    Publication date: May 6, 2021
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Makoto YOKOYAMA, Junichi YAMADA
  • Publication number: 20210098560
    Abstract: A display device including: a driver outside a display area; a special-shape portion on an edge of the display area, the special-shape portion being shaped like a line that is curved or oblique to an extension direction of signal lines in the display area; a plurality of first-type circuit blocks outside the special-shape portion, each of the first-type circuit blocks including a unit circuit for the driver in a rectangular region having a first side parallel to the extension direction and a second side perpendicular to, and shorter than, the first side; and a plurality of second-type circuit blocks outside the special-shape portion, each of the second-type circuit blocks including a unit circuit for the driver in a rectangular region obtained by rotating the previous rectangular region by 90°.
    Type: Application
    Filed: April 12, 2018
    Publication date: April 1, 2021
    Inventors: TAKEHIKO KAWAMURA, JUNICHI YAMADA, MAKOTO YOKOYAMA
  • Publication number: 20210048699
    Abstract: Provided is a display device including a display panel which allows a curvature portion thereof to be narrowed near a terminal portion even when circuit blocks are arranged in the curvature portion. For a data line in the form of a polyline consisting of a plurality of short straight line segments in a first curvature portion 12a of a display panel 10, as the distance from a terminal portion 16 increases, the slant angle of each straight line segment increases, the number of data lines d decreases, and hence the width of a data line area decreases. Accordingly, the number of unit circuit blocks 70 in a parallel circuit block 80 disposed in a circuit area can be increased by widening the circuit area in proportion to the decrease in the width of the data line area.
    Type: Application
    Filed: March 16, 2018
    Publication date: February 18, 2021
    Inventors: JUNICHI YAMADA, MAKOTO YOKOYAMA, NAOKI UEDA
  • Publication number: 20210027716
    Abstract: Provided is a display device including an irregularly shaped display panel that allows a frame area to be narrowed by utilizing the frame area in a cutout portion. Some emission circuits 61 that respectively correspond to scan circuits 51 arranged in a first curvature portion 12a are arranged in a part of a second side portion 13b that is near the first curvature portion 12a, and remaining emission circuits 61 are arranged in a first notch side portion 14a. Accordingly, the emission circuits arranged in the first notch side portion 14a have lines connected to second emission control lines EMb in a second display area 15B from the first notch side portion 14a side, resulting in a fewer number of lines extending into the first curvature portion 12a.
    Type: Application
    Filed: March 28, 2018
    Publication date: January 28, 2021
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: JUNICHI YAMADA, MAKOTO YOKOYAMA
  • Publication number: 20210027718
    Abstract: One of a plurality of data signal lines or one of a plurality of control lines that is electrically coupled to a first lead wiring line, and another one of the plurality of data signal lines or another one of the plurality of control lines that is electrically coupled to a second lead wiring line are adjacent to each other. The first lead wiring line is provided in a first metal layer. The second lead wiring line is provided in a second metal layer being a layer different from the first metal layer. The first lead wiring line and the second lead wiring line are superposed on one another through intermediation of an inorganic insulating film.
    Type: Application
    Filed: March 30, 2018
    Publication date: January 28, 2021
    Inventors: MAKOTO YOKOYAMA, JUNICHI YAMADA
  • Publication number: 20210028270
    Abstract: A nick is disposed in a display region so as to partly cut the display region. A first routed wire is routed from the display region toward the nick. The first routed wire is included in a first metal layer. A first conductive film is included in a second metal layer. The first routed wire and the first conductive film overlap each other via an inorganic insulating film.
    Type: Application
    Filed: March 30, 2018
    Publication date: January 28, 2021
    Inventors: MAKOTO YOKOYAMA, JUNICHI YAMADA
  • Publication number: 20210020734
    Abstract: A first metal layer, an inorganic insulating film, and a second metal layer are provided. A first wiring line led to a peripheral edge of a cutout portion is provided in the first metal layer. A second wiring line led to the peripheral edge of the cutout portion is provided in the second metal layer. The first lead wiring line and the second lead wiring line overlap each other through intermediation of the inorganic insulating film.
    Type: Application
    Filed: March 30, 2018
    Publication date: January 21, 2021
    Inventors: MAKOTO YOKOYAMA, JUNICHI YAMADA
  • Publication number: 20210020111
    Abstract: To provide a display device including a display panel having an irregular shape capable of narrowing the frame even in a case where two types of drive circuits are arranged. In a display panel having an irregular shape including a frame formed from straight line regions and curved line regions, scanning circuits and emission circuits are separated. Then, the separated scanning circuits are arranged in a first corner portion, which is the curved line region of the display panel, while being shifted along an outer peripheral edge of a display region, and the emission circuits are arranged in a row on a second side, which is the straight line region.
    Type: Application
    Filed: March 19, 2018
    Publication date: January 21, 2021
    Inventors: JUNICHI YAMADA, MAKOTO YOKOYAMA
  • Patent number: 10861392
    Abstract: Provided are a display device drive method and a display device, both of which allow a pixel circuit to be discharged without leaving any electric charge in an OFF sequence for powering off the display device. During an OFF sequence period, a first node N1 is set to a first ground potential Vgnd1, which is a potential higher than an initialization potential Vini. As a result, even when a second ground potential Vgnd2 is supplied through a data line Dj to a second conductive terminal of a drive transistor T1, a gate terminal of the drive transistor T1 is not charged with a gate-to-source voltage Vgs. Therefore, an organic EL display device 1 is powered off with the gate terminal of the drive transistor T1 being charged with the first ground potential Vgnd1 leaving no electric charge in a pixel circuit 11 after the power off.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: December 8, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Makoto Yokoyama, Fumiyuki Kobayashi, Junichi Yamada
  • Patent number: 10706803
    Abstract: Provided is a shift register circuit capable of preventing occurrence of malfunction caused by a threshold shift of a thin-film transistor due to an influence of external light. A unit circuit constituting each stage of the shift register circuit includes a plurality of thin-film transistors. The plurality of thin-film transistors are categorized into a first group (T2, T4, T9) whose on-off state is controlled at relatively high on-duty and a second group (T1, T3, T5, T6, T7, T8) whose on-off state is controlled at relatively low on-duty. In such a configuration, a light shielding film (LS) is provided only for the thin-film transistor included in one of the first group and the second group.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shige Furuta, Takahiro Yamaguchi, Junichi Yamada, Hidekazu Yamanaka, Yasushi Sasaki, Yuhichiroh Murakami
  • Publication number: 20200098316
    Abstract: Provided are a display device drive method and a display device, both of which allow a pixel circuit to be discharged without leaving any electric charge in an OFF sequence for powering off the display device. During an OFF sequence period, a first node N1 is set to a first ground potential Vgnd1, which is a potential higher than an initialization potential Vini. As a result, even when a second ground potential Vgnd2 is supplied through a data line Dj to a second conductive terminal of a drive transistor T1, a gate terminal of the drive transistor T1 is not charged with a gate-to-source voltage Vgs. Therefore, an organic EL display device 1 is powered off with the gate terminal of the drive transistor T1 being charged with the first ground potential Vgnd1 leaving no electric charge in a pixel circuit 11 after the power off.
    Type: Application
    Filed: March 22, 2017
    Publication date: March 26, 2020
    Inventors: Makoto YOKOYAMA, Fumiyuki KOBAYASHI, Junichi YAMADA
  • Patent number: 10554065
    Abstract: A battery control apparatus includes a reduced electricity cost analysis unit that obtains a discharge electric power cost at a discharge time and a charge electric power cost at a charge time of a battery, based on a basic cost and a unit cost of an electricity bill, and obtains a reduced electricity cost in which the charge electric power cost is subtracted from the discharge electric power cost for every discharge depth of the battery; an introduction cost analysis unit that calculates an introduction cost of the battery for every discharge depth of the battery; and a charge and discharge depth optimization unit that obtains a difference of the reduced electricity cost and the introduction cost for every discharge depth of the battery, and determines a charge and discharge depth of the battery based on the difference. The discharge of the battery is performed at the determined charge and discharge depth.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: February 4, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Noriyuki Miyake, Yasushi Tomita, Tsutomu Kawamura, Hirotaka Takahashi, Kenichi Kuwabara, Daisuke Hisajima, Junichi Yamada
  • Publication number: 20190331974
    Abstract: Regarding a variant-form display (typically, a display device having a shape in which a non-display region is provided between display regions), it achieves a narrower picture-frame than conventional displays. In a display device having a non-rectangular display region, sub gate drivers are provided in a region where bypass wiring lines are conventionally disposed, for example, as follows. In a display device having a right-angled U-shaped display region having two projecting portions (a left projecting portion and a right projecting portion, a sub gate driver for driving some gate bus lines disposed in the left projecting portion is provided, in a region in a recessed portion, in a vicinity of the left projecting portion, and a sub gate driver for driving some gate bus lines disposed in the right projecting portion is provided, in a region in the recessed portion, in a vicinity of the right projecting portion.
    Type: Application
    Filed: August 1, 2017
    Publication date: October 31, 2019
    Inventors: Shige FURUTA, Yasushi SASAKI, Yuhichiroh MURAKAMI, Takahiro YAMAGUCHI, Junichi YAMADA, Hidekazu YAMANAKA
  • Patent number: 10214441
    Abstract: Provided is a cutting device including a machining table configured to float a workpiece having a plate shape, a laser radiation unit configured to radiate a laser beam onto the workpiece, a coolant injection unit configured to inject a coolant onto the workpiece, and a moving device configured to relatively move the workpiece with respect to the laser radiation unit and the coolant injection unit in a preset direction. In the cutting device, a scattering member configured to receive injection of the coolant from the coolant injection unit and scatter the coolant is installed at the machining table in front of the workpiece in a moving direction in which the workpiece relatively moves.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: February 26, 2019
    Assignee: IHI CORPORATION
    Inventor: Junichi Yamada
  • Publication number: 20180149911
    Abstract: A drive circuit of a display device includes a TFT having a source electrode 15, a drain electrode 14, and a gate electrode 13. Provided is an electrically isolated light-shielding film 12 which has a main body portion for shielding a channel portion of the TFT, and an extension portion 20 formed integrally with the main body portion. An auxiliary capacitor C2 is formed by overlapping, in a planar view, the extension portion 20 with an electrode member 21 formed integrally with the source electrode 15. In place of the electrode member 21, an electrode member formed in a same layer as the channel portion and connected to the source electrode 15, an electrode member connected to one conduction electrode of another TFT, or an electrode member formed integrally with the gate electrode 13 may be used. With this, a small-area and low-cost drive circuit including a light-shielded thin film transistor is provided.
    Type: Application
    Filed: May 18, 2016
    Publication date: May 31, 2018
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: TAKAHIRO YAMAGUCHI, SHIGE FURUTA, JUNICHI YAMADA, HIDEKAZU YAMANAKA, YUHICHIROH MURAKAMI, YASUSHI SASAKI
  • Publication number: 20180144702
    Abstract: Provided is a shift register circuit capable of preventing occurrence of malfunction caused by a threshold shift of a thin-film transistor due to an influence of external light. A unit circuit constituting each stage of the shift register circuit includes a plurality of thin-film transistors. The plurality of thin-film transistors are categorized into a first group (T2, T4, T9) whose on-off state is controlled at relatively high on-duty and a second group (T1, T3, T5, T6, T7, T8) whose on-off state is controlled at relatively low on-duty. In such a configuration, a light shielding film (LS) is provided only for the thin-film transistor included in one of the first group and the second group.
    Type: Application
    Filed: May 18, 2016
    Publication date: May 24, 2018
    Inventors: SHIGE FURUTA, TAKAHIRO YAMAGUCHI, JUNICHI YAMADA, HIDEKAZU YAMANAKA, YASUSHI SASAKI, YUHICHIROH MURAKAMI
  • Publication number: 20170005483
    Abstract: A battery control apparatus includes a reduced electricity cost analysis unit that obtains a discharge electric power cost at a discharge time and a charge electric power cost at a charge time of a battery, based on a basic cost and a unit cost of an electricity bill, and obtains a reduced electricity cost in which the charge electric power cost is subtracted from the discharge electric power cost for every discharge depth of the battery; an introduction cost analysis unit that calculates an introduction cost of the battery for every discharge depth of the battery; and a charge and discharge depth optimization unit that obtains a difference of the reduced electricity cost and the introduction cost for every discharge depth of the battery, and determines a charge and discharge depth of the battery based. on the difference. The discharge of the battery is performed at the determined charge and discharge depth.
    Type: Application
    Filed: September 10, 2014
    Publication date: January 5, 2017
    Inventors: Noriyuki MIYAKE, Yasushi TOMITA, Tsutomu KAWAMURA, Hirotaka TAKAHASHI, Kenichi KUWABARA, Daisuke HISAJIMA, Junichi YAMADA
  • Publication number: 20150359102
    Abstract: Electrical characteristics of a mounting board over which a semiconductor device is mounted is improved. A mounting board (wiring board) includes a plurality of first through holes and second through holes extending from its upper surface bearing a semiconductor device (semiconductor package) to its lower surface and through-hole wirings formed in the respective through holes. The mounting board has a capacitor arranged on its lower surface and electrically connected with the semiconductor device via second electrodes. Among a plurality of first electrodes formed on the upper surface of the mounting board, the several first electrodes to be connected with the capacitor are connected with one wiring formed in a first through hole with a larger diameter than a signal transmission path.
    Type: Application
    Filed: August 19, 2015
    Publication date: December 10, 2015
    Inventors: Mitsuyuki KUBO, Junichi YAMADA, Hiroshi HOMMA
  • Patent number: 9129914
    Abstract: Electrical characteristics of a mounting board over which a semiconductor device is mounted is improved. A mounting board (wiring board) includes a plurality of first through holes and second through holes extending from its upper surface bearing a semiconductor device (semiconductor package) to its lower surface and through-hole wirings formed in the respective through holes. The mounting board has a capacitor arranged on its lower surface and electrically connected with the semiconductor device via second electrodes. Among a plurality of first electrodes formed on the upper surface of the mounting board, the several first electrodes to be connected with the capacitor are connected with one wiring formed in a first through hole with a larger diameter than a signal transmission path.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: September 8, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Mitsuyuki Kubo, Junichi Yamada, Hiroshi Homma
  • Publication number: 20150246840
    Abstract: Provided is a workpiece cutting method of cutting a workpiece in which a reinforcement layer to which compression stress is applied is stacked on a surface of a non-reinforcement layer in a thickness direction of the workpiece, the workpiece cutting method including a process of continuously heating the surface of the reinforcement layer in a direction perpendicular to the thickness direction and transferring heat to the reinforcement layer and the non-reinforcement layer; and a process of injecting a cooling medium to a surface of the workpiece after heating, and generating thermal stress equal to or larger than breaking stress of the non-reinforcement layer in a boundary portion of the non-reinforcement layer with respect to the reinforcement layer. According to the workpiece cutting method, the workpiece can be rapidly cut, and deterioration of quality of the cutting portion can be suppressed.
    Type: Application
    Filed: May 15, 2015
    Publication date: September 3, 2015
    Applicant: IHI Corporation
    Inventors: Norihito KAWAGUCHI, Junichi YAMADA, Tomoo KUSUMI, Toshiaki SAITO