Abstract: A non-volatile semiconductor memory device is provided with: a first memory cell including a floating gate transistor; a first bitline connected to a diffusion layer which is used as a source of the first memory cell; a second bitline connected to a diffusion layer which is used as a drain of the first memory cell; a first reference cell including a floating gate transistor; a third bitline electrically isolated from the first bitline and connected to a diffusion layer which is used as a source of the first reference cell; a read circuit identifying data stored in the first memory cell in response to a memory cell signal received from the first memory cell through the second bitline and a reference signal received from the first reference cell through the fourth bitline; and a bitline level controller controlling a voltage level of the third bitline.

Abstract: A lamp including a plurality of light emitting devices and heat sinks can be configured to dissipate heat generated by the plurality of light emitting devices. The heat sinks can be branched into a generally Y-shaped configuration as viewed in a section that includes a primary optical axis of the vehicle lamp. One of the light emitting devices is connected to one of the branched parts of the heat sinks. Another light emitting device is connected to the other branched part of the heat sinks.

Abstract: Realizes a structure for a transreflective liquid crystal display device in which one pixel is defined by four or more picture elements, the structure providing a high aperture ratio and being suitable for display for which the transmission mode is prioritized. A liquid crystal display device according to the present invention is a transreflective liquid crystal display device, comprising a plurality of picture elements including a first picture element, a second picture element, a third picture element and a fourth picture element for displaying different colors from one another; in which each of the plurality of picture elements includes a transmission area for providing display in a transmission mode and a reflection area for providing display in a reflection mode. Each picture element includes a mesh portion shaped to be meshable with an adjacent picture element; and the reflection area of each picture element is located in the mesh portion.

Abstract: A non-volatile semiconductor memory device includes a memory cell, and a reference cell including a same structure as the memory cell. A detecting circuit detects a timing when a voltage of a reference bit line connected with the reference cell becomes lower than or equal to a setting voltage, and generates a control signal in response to the detection of the timing. A sense amplifier senses and amplifies a difference between a voltage of a bit line connected with the memory cell and a reference voltage in response to the control signal.

Abstract: A non-volatile semiconductor memory device is provided with: a first memory cell including a floating gate transistor; a first bitline connected to a diffusion layer which is used as a source of the first memory cell; a second bitline connected to a diffusion layer which is used as a drain of the first memory cell; a first reference cell including a floating gate transistor; a third bitline electrically isolated from the first bitline and connected to a diffusion layer which is used as a source of the first reference cell; a read circuit identifying data stored in the first memory cell in response to a memory cell signal received from the first memory cell through the second bitline and a reference signal received from the first reference cell through the fourth bitline; and a bitline level controller controlling a voltage level of the third bitline.

Abstract: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage.

Abstract: A display device includes a source line for supplying a display signal, a display pixel electrode, and a TFT for switching an electrical connection between the source line and the pixel electrode. The TFT includes a source electrode electrically connected to the source line, a drain electrode electrically connected to the pixel electrode, and a gate electrode for controlling an electrical connection between the source electrode and the drain electrode. A first auxiliary capacitor electrode and a second auxiliary capacitor electrode are connected to the drain electrode and respective connection portions between the drain electrode and the auxiliary capacitor electrodes are formed of a semiconductor material.

Abstract: A system for managing energy consumption has a data storage module, a calculation module and an operation planning module. The data storage module stores an operational past record of a unit belonging to a facility to be managed by the system. The calculation module calculates wasteful energy consumption for the unit based on the operational past record stored in the data storage module. The operation planning module generates an operational plan for the unit belonging to the facility based on the wasteful energy consumption calculated by the calculation module.

Abstract: A method of driving source lines is arranged as follows: One output signal line S61 of a source driver is connected to a plurality of lines corresponding to respective source lines SR7 through SB12, and these source lines from SR7 (starting data line) to SB12 (terminating data line) are grouped as one block (group). In each block, a signal voltage of a divided output is supplied to the source lines during a first horizontal period T, while a signal voltage whose polarity is opposite to that of the aforesaid output is supplied to the source lines in a second horizontal period that is after the first horizontal period. In each of the horizontal periods, the source lines SR7 through SB12 are subjected to sequential selection. In addition to this, the source line SB12 is selected before turning the source line SR7 off.

Abstract: A non-volatile semiconductor memory device includes a memory cell, and a reference cell including a same structure as the memory cell. A detecting circuit detects a timing when a voltage of a reference bit line connected with the reference cell becomes lower than or equal to a setting voltage, and generates a control signal in response to the detection of the timing. A sense amplifier senses and amplifies a difference between a voltage of a bit line connected with the memory cell and a reference voltage in response to the control signal.

Abstract: A method of driving source lines is arranged as follows: One output signal line S61 of a source driver is connected to a plurality of lines corresponding to respective source lines SR7 through SB12, and these source lines from SR7 (starting data line) to SB12 (terminating data line) are grouped as one block (group). In each block, a signal voltage of a divided output is supplied to the source lines during a first horizontal period T, while a signal voltage whose polarity is opposite to that of the aforesaid output is supplied to the source lines in a second horizontal period that is after the first horizontal period. In each of the horizontal periods, the source lines SR7 through SB12 are subjected to sequential selection. In addition to this, the source line SB12 is selected before turning the source line SR7 off.

Abstract: A display device includes a source line for supplying a display signal, a display pixel electrode, and a TFT for switching an electrical connection between the source line and the pixel electrode. The TFT includes a source electrode electrically connected to the source line, a drain electrode electrically connected to the pixel electrode, and a gate electrode for controlling an electrical connection between the source electrode and the drain electrode. A first auxiliary capacitor electrode and a second auxiliary capacitor electrode are connected to the drain electrode and respective connection portions between the drain electrode and the auxiliary capacitor electrodes are formed of a semiconductor material.

Abstract: In a semiconductor memory incorporating therein a circuit for relieving a defective memory cell, a memory cell array constituted of a number of main memory cells MC00 to MCij is added with one column of redundant memory cells MC0j+1 to MCij+1 and one word line of substitution information storing memory cells MCRA0 to MCRAj+1. In only a first cycle after the power supply is turned on, the substitution information DR0 to DRj is read out from the substitution information storing memory cells by use of a writing/reading circuit associated with the main memory cells, and is transferred to and held in a control circuit. In a second and succeeding cycles, the control circuit generates Y selection circuit control signals CS0 to CSj on the basis of the substitution information held in the control circuit, and a Y selection circuit is controlled by the control signals CS0 to CSj so as to selectively connect the columns other than a defective column to an input/output line.

Abstract: A system for managing energy consumption has a data storage module, a calculation module and an operation planning module. The data storage module stores an operational past record of a unit belonging to a facility to be managed by the system. The calculation module calculates wasteful energy consumption for the unit based on the operational past record stored in the data storage module. The operation planning module generates an operational plan for the unit belonging to the facility based on the wasteful energy consumption calculated by the calculation module.

Abstract: In a semiconductor memory incorporating therein a circuit for relieving a defective memory cell, a memory cell array constituted of a number of main memory cells MC00 to MCij is added with one column of redundant memory cells MC0j+1 to MCij+1 and one word line of substitution information storing memory cells MCRA0 to MCRAj+1. In only a first cycle after the power supply is turned on, the substitution information DR0 to DRj is read out from the substitution information storing memory cells by use of a writing/reading circuit associated with the main memory cells, and is transferred to and held in a control circuit. In a second and succeeding cycles, the control circuit generates Y selection circuit control signals CS0 to CSj on the basis of the substitution information held in the control circuit, and a Y selection circuit is controlled by the control signals CS0 to CSj so as to selectively connect the columns other than a defective column to an input/output line.