Patents by Inventor Junichiro Noda
Junichiro Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230197125Abstract: A memory system includes a controller, a plurality of memory devices, and a signal wiring. The signal wiring is connected between the controller and the volatile memory devices and configuring a fly-by topology. At least one of the memory devices includes a memory cell array, a processing circuit configured to control the memory cell array, an input buffer through which a signal from the controller is transmitted to the processing circuit, and a resistor circuit connected between the input buffer and the signal wiring. The resistor circuit has a resistance value corresponding to a parasitic capacitance of the input buffer.Type: ApplicationFiled: August 30, 2022Publication date: June 22, 2023Inventor: Junichiro NODA
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Publication number: 20150061734Abstract: According to one embodiment, a first pull-down transistor, a mode switching circuit, and a leak-cut circuit are provided. The first pull-down transistor pulls down an input/output terminal. The mode switching circuit controls on and off of the first pull-down transistor based on an enable signal. The leak-cut circuit turns off the first pull-down transistor when a power supply of the mode switching circuit is shut down.Type: ApplicationFiled: March 6, 2014Publication date: March 5, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yosuke Ogawa, Akira Iwata, Junichiro Noda
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Patent number: 7365555Abstract: A semiconductor device has a boosting circuit configured to generate a boosting potential to an output line. An internal circuit is supplied with the boosting potential from the boosting circuit via the output line. A test line is connected to the output line. A control circuit is arranged between the output line and the test line and configured to shut off a current flowing into the test line from the output line during a boosting operation of the boosting circuit.Type: GrantFiled: July 21, 2006Date of Patent: April 29, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Junichiro Noda
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Publication number: 20060255823Abstract: A semiconductor device has a boosting circuit configured to generate a boosting potential to an output line. An internal circuit is supplied with the boosting potential from the boosting circuit via the output line. A test line is connected to the output line. A control circuit is arranged between the output line and the test line and configured to shut off a current flowing into the test line from the output line during a boosting operation of the boosting circuit.Type: ApplicationFiled: July 21, 2006Publication date: November 16, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Junichiro Noda
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Patent number: 7123501Abstract: A semiconductor memory device includes a memory cell section having at least one memory cell using a cell transistor and a ferroelectric capacitor to store data. A sense amplifier is connected to the memory cell through a bit line. The device further includes an error checking and correction circuit which checks and corrects an error of data, which is read out of the memory cell by the sense amplifier, through the bit line.Type: GrantFiled: September 10, 2004Date of Patent: October 17, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Junichiro Noda
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Patent number: 7098681Abstract: A semiconductor device has a boosting circuit configured to generate a boosting potential to an output line. An internal circuit is supplied with the boosting potential from the boosting circuit via the output line. A test line is connected to the output line. A control circuit is arranged between the output line and the test line and configured to shut off a current flowing into the test line from the output line during a boosting operation of the boosting circuit.Type: GrantFiled: July 23, 2004Date of Patent: August 29, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Junichiro Noda
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Patent number: 6999353Abstract: A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.Type: GrantFiled: October 20, 2004Date of Patent: February 14, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Junichiro Noda, Tamio Ikehashi, Kenichi Imamiya
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Publication number: 20050094476Abstract: A semiconductor memory device includes a memory cell section having at least one memory cell using a cell transistor and a ferroelectric capacitor to store data. A sense amplifier is connected to the memory cell through a bit line. The device further includes an error checking and correction circuit which checks and corrects an error of data, which is read out of the memory cell by the sense amplifier, through the bit line.Type: ApplicationFiled: September 10, 2004Publication date: May 5, 2005Inventor: Junichiro Noda
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Publication number: 20050058006Abstract: A semiconductor device has a boosting circuit configured to generate a boosting potential to an output line. An internal circuit is supplied with the boosting potential from the boosting circuit via the output line. A test line is connected to the output line. A control circuit is arranged between the output line and the test line and configured to shut off a current flowing into the test line from the output line during a boosting operation of the boosting circuit.Type: ApplicationFiled: July 23, 2004Publication date: March 17, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Junichiro Noda
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Publication number: 20050052930Abstract: A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.Type: ApplicationFiled: October 20, 2004Publication date: March 10, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Junichiro Noda, Tamio Ikehashi, Kenichi Imamiya
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Patent number: 6845047Abstract: An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.Type: GrantFiled: September 22, 2003Date of Patent: January 18, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Tamio Ikehashi, Kenichi Imamiya, Junichiro Noda
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Patent number: 6826116Abstract: A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.Type: GrantFiled: January 6, 2004Date of Patent: November 30, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Junichiro Noda, Tamio Ikehashi, Kenichi Imamiya
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Publication number: 20040141375Abstract: A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.Type: ApplicationFiled: January 6, 2004Publication date: July 22, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Junichiro Noda, Tamio Ikehashi, Kenichi Imamiya
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Patent number: 6731538Abstract: A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.Type: GrantFiled: October 16, 2002Date of Patent: May 4, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Junichiro Noda, Tamio Ikehashi, Kenichi Imamiya
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Publication number: 20040057326Abstract: An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.Type: ApplicationFiled: September 22, 2003Publication date: March 25, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Tamio Ikehashi, Kenichi Imamiya, Junichiro Noda
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Patent number: 6674668Abstract: An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.Type: GrantFiled: July 3, 2002Date of Patent: January 6, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Tamio Ikehashi, Kenichi Imamiya, Junichiro Noda
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Publication number: 20030151955Abstract: A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.Type: ApplicationFiled: October 16, 2002Publication date: August 14, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Junichiro Noda, Tamio Ikehashi, Kenichi Imamiya
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Publication number: 20020196667Abstract: An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.Type: ApplicationFiled: July 3, 2002Publication date: December 26, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Tamio Ikehashi, Kenichi Imamiya, Junichiro Noda
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Patent number: 6438038Abstract: An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.Type: GrantFiled: December 26, 2000Date of Patent: August 20, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Tamio Ikehashi, Kenichi Imamiya, Junichiro Noda
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Patent number: 6400604Abstract: A nonvolatile semiconductor memory device having a data reprogram mode comprising a memory cell array in which a plurality of memory cells are arranged in a matrix form, a page buffer storing one page data to be programmed to memory cells which are selected in accordance with a page address signal, an internal column address generating circuit for generating column addresses of the one page with inputting the page address signal in order to transfer the one data stored in the page buffer to the memory cells, a column decoder receiving the column addresses from the internal column address generating circuit, and a control circuit having a data reprogram mode which is a mode for erasing one page data stored in the memory cells which are selected in accordance with the page address signal and continuously programming the one page data stored in the page buffer to the memory cells which are selected.Type: GrantFiled: January 19, 2001Date of Patent: June 4, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Junichiro Noda