Abstract: A semiconductor memory device invention having a data latch circuit disclosed in the present invention, comprising a plurality of bit lines to which a reprogramable memory cell is connected, a data bus on which data is transferred, a latch circuit having latching the data transferred on the data bus, a read our circuit connected to the data bus and a data transfer circuit group having an ability to directly transfer the data latched in the latch circuit, to the read our circuit without transferred to the memory cell.

Abstract: A nonvolatile semiconductor memory device having a data reprogram mode comprising a memory cell array in which a plurality of memory cells are arranged in a matrix form, a page buffer storing one page data to be programmed to memory cells which are selected in accordance with a page address signal, an internal column address generating circuit for generating column addresses of the one page with inputting the page address signal in order to transfer the one data stored in the page buffer to the memory cells, a column decoder receiving the column addresses from the internal column address generating circuit, and a control circuit having a data reprogram mode which is a mode for erasing one page data stored in the memory cells which are selected in accordance with the page address signal and continuously programming the one page data stored in the page buffer to the memory cells which are selected.

Abstract: An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

Abstract: A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.

Abstract: A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.

Abstract: A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.